Journal of Low Power Electronics and Applications最新文献

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An Ultra-Low-Voltage Approach to Accurately Set the Quiescent Current of Digital Standard Cells Used for Analog Design and Its Application on an Inverter-Based Operational Transconductance Amplifier 准确设置用于模拟设计的数字标准单元静态电流的超低电压方法及其在基于逆变器的运算跨导放大器上的应用

Journal of Low Power Electronics and Applications Pub Date : 2024-07-24 DOI: 10.3390/jlpea14030039

Riccardo Della Sala, F. Centurelli, G. Scotti

{"title":"An Ultra-Low-Voltage Approach to Accurately Set the Quiescent Current of Digital Standard Cells Used for Analog Design and Its Application on an Inverter-Based Operational Transconductance Amplifier","authors":"Riccardo Della Sala, F. Centurelli, G. Scotti","doi":"10.3390/jlpea14030039","DOIUrl":"https://doi.org/10.3390/jlpea14030039","url":null,"abstract":"An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell’s quiescent current to a multiple of a reference current and each cell’s static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA.","PeriodicalId":506045,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":"36 3","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141810080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Advancing Smart Lighting: A Developmental Approach to Energy Efficiency through Brightness Adjustment Strategies 推进智能照明：通过亮度调节策略提高能效的发展方法

Journal of Low Power Electronics and Applications Pub Date : 2024-01-15 DOI: 10.3390/jlpea14010006

V. Widartha, Ilkyeun Ra, Su-Yeon Lee, Chang-Soo Kim

引用次数: 0

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism 具有动态端口配置和刷新机制的多端口 GC-eDRAM 位元组

Journal of Low Power Electronics and Applications Pub Date : 2024-01-04 DOI: 10.3390/jlpea14010002

R. Golman, R. Giterman, A. Teman

{"title":"Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism","authors":"R. Golman, R. Giterman, A. Teman","doi":"10.3390/jlpea14010002","DOIUrl":"https://doi.org/10.3390/jlpea14010002","url":null,"abstract":"Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher power due to larger memory bitcells. Gain-cell eDRAM is a high-density alternative for multi-ported operation with a small silicon footprint. However, conventional gain-cell memories have limited data availability, as they require periodic refresh operations to maintain their data. In this paper, we propose a novel multi-ported gain-cell design, which provides up-to N read ports and M independent write ports (NRMW). In addition, the proposed design features a configurable mode of operation, supporting a hidden refresh mechanism for improved memory availability, as well as a novel opportunistic refresh port approach. An 8kbit memory macro was implemented using a four-transistor bitcell with four ports (2R2W) in a 28 nm FD-SOI technology, offering up-to a 3× reduction in bitcell area compared to other dual-ported SRAM memory options, while also providing 100% memory availability, as opposed to conventional dynamic memories, which are hindered by limited availability.","PeriodicalId":506045,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":"63 2","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139386887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0