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Journal of Low Power Electronics最新文献

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ULV and ULP Operational Amplifiers for Active-RC Filters 用于有源rc滤波器的ULV和ULP运算放大器
Journal of Low Power Electronics Pub Date : 2021-10-08 DOI: 10.1007/978-3-030-90103-5_2
L. Severo, W. Van Noije
{"title":"ULV and ULP Operational Amplifiers for Active-RC Filters","authors":"L. Severo, W. Van Noije","doi":"10.1007/978-3-030-90103-5_2","DOIUrl":"https://doi.org/10.1007/978-3-030-90103-5_2","url":null,"abstract":"","PeriodicalId":43794,"journal":{"name":"Journal of Low Power Electronics","volume":"12 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82682549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Single Stage OTA and Negative Transconductance Compensation 单级OTA和负跨导补偿
Journal of Low Power Electronics Pub Date : 2021-10-08 DOI: 10.1007/978-3-030-90103-5_3
L. Severo, W. Van Noije
{"title":"Single Stage OTA and Negative Transconductance Compensation","authors":"L. Severo, W. Van Noije","doi":"10.1007/978-3-030-90103-5_3","DOIUrl":"https://doi.org/10.1007/978-3-030-90103-5_3","url":null,"abstract":"","PeriodicalId":43794,"journal":{"name":"Journal of Low Power Electronics","volume":"35 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90593022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and Experimental Results 设计与实验结果
Journal of Low Power Electronics Pub Date : 2021-10-08 DOI: 10.1007/978-3-030-90103-5_5
L. Severo, W. Van Noije
{"title":"Design and Experimental Results","authors":"L. Severo, W. Van Noije","doi":"10.1007/978-3-030-90103-5_5","DOIUrl":"https://doi.org/10.1007/978-3-030-90103-5_5","url":null,"abstract":"","PeriodicalId":43794,"journal":{"name":"Journal of Low Power Electronics","volume":"45 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73046197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Selected Peer Reviewed Articles from the 17th "IEEE Latin-American Test Symposium," Foz do Iguaçu, Brazil, April 6–8, 2016 2016年4月6日至8日，第17届“IEEE拉丁美洲测试研讨会”，巴西，Foz do igua<e:1>
Journal of Low Power Electronics Pub Date : 2016-12-01 DOI: 10.1166/JOLPE.2016.1461
L. Poehls
{"title":"Selected Peer Reviewed Articles from the 17th \"IEEE Latin-American Test Symposium,\" Foz do Iguaçu, Brazil, April 6–8, 2016","authors":"L. Poehls","doi":"10.1166/JOLPE.2016.1461","DOIUrl":"https://doi.org/10.1166/JOLPE.2016.1461","url":null,"abstract":"","PeriodicalId":43794,"journal":{"name":"Journal of Low Power Electronics","volume":"12 1","pages":"394-394"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64643207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Ultra-Low Power Charge Redistribution Successive Approximation Register A/D Converter for Biomedical Applications. 生物医学应用的超低功率电荷再分配逐次逼近寄存器A/D转换器。
Journal of Low Power Electronics Pub Date : 2016-12-01 DOI: 10.1166/jolpe.2016.1452
Santosh Koppa, Manouchehr Mohandesi, Eugene John
{"title":"An Ultra-Low Power Charge Redistribution Successive Approximation Register A/D Converter for Biomedical Applications.","authors":"Santosh Koppa,&nbsp;Manouchehr Mohandesi,&nbsp;Eugene John","doi":"10.1166/jolpe.2016.1452","DOIUrl":"https://doi.org/10.1166/jolpe.2016.1452","url":null,"abstract":"<p><p>Power consumption is one of the key design constraints in biomedical devices such as pacemakers that are powered by small non rechargeable batteries over their entire life time. In these systems, Analog to Digital Convertors (ADCs) are used as interface between analog world and digital domain and play a key role. In this paper we present the design of an 8-bit Charge Redistribution Successive Approximation Register (CR-SAR) analog to digital converter in standard TSMC 0.18μm CMOS technology for low power and low data rate devices such as pacemakers. The 8-bit optimized CR-SAR ADC achieves low power of less than 250nW with conversion rate of 1KB/s. This ADC achieves integral nonlinearity (INL) and differential nonlinearity (DNL) less than 0.22 least significant bit (LSB) and less than 0.04 LSB respectively as compared to the standard requirement for the INL and DNL errors to be less than 0.5 LSB. The designed ADC operates at 1V supply voltage converting input ranging from 0V to 250mV.</p>","PeriodicalId":43794,"journal":{"name":"Journal of Low Power Electronics","volume":"12 4","pages":"385-393"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5851472/pdf/nihms923646.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"35925764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Reducing Power and Cycle Requirement for FFT of ECG Signals through Low Level Arithmetic Optimizations for Cardiac Implantable Devices. 通过心脏植入装置低电平算法优化降低心电信号FFT功率和周期要求。
Journal of Low Power Electronics Pub Date : 2016-03-01 DOI: 10.1166/jolpe.2016.1423
Safwat Mostafa, Eugene John
{"title":"Reducing Power and Cycle Requirement for FFT of ECG Signals through Low Level Arithmetic Optimizations for Cardiac Implantable Devices.","authors":"Safwat Mostafa,&nbsp;Eugene John","doi":"10.1166/jolpe.2016.1423","DOIUrl":"https://doi.org/10.1166/jolpe.2016.1423","url":null,"abstract":"<p><p>The Fast Fourier Transform or FFT remains to be the de facto standard in almost all disciplines for computing discrete Fourier transform. In embedded biomedical applications, efficient signal processing algorithms such as FFT for spectrum analysis are indispensable. The FFT is an O(Nlog<sub>2</sub>N) algorithm which requires complex multiplication and addition using floating point numbers. On extremely power constrained embedded systems such as cardiac pacemakers, floating point operations are very cycle intensive and costly in terms of power. This work aims to exploit the repetitive nature of the Electrocardiogram (ECG) to reduce the number of total arithmetic operations required to execute a 128 point FFT routine. Using the simple concept of lookup tables, the proposed algorithm is able to improve both the performance and energy footprint for computing the FFT of the ECG data. An increase of 9.22% in computational speed and an improvement of 10.1% in battery life on a 32 bit embedded platform for a standard split-radix-2 FFT routine is achieved. The concept is tested using actual ECG data collected from PhysioNet.</p>","PeriodicalId":43794,"journal":{"name":"Journal of Low Power Electronics","volume":"12 1","pages":"21-29"},"PeriodicalIF":0.0,"publicationDate":"2016-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5846710/pdf/nihms923653.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"35915992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Locking and Pulling in Injection-Locked LC-CMOS Dividers 锁定和拉入注入锁定LC-CMOS分频器
Journal of Low Power Electronics Pub Date : 2013-08-01 DOI: 10.1166/JOLPE.2013.1252
A. Buonomo, A. L. Schiavo
{"title":"Locking and Pulling in Injection-Locked LC-CMOS Dividers","authors":"A. Buonomo, A. L. Schiavo","doi":"10.1166/JOLPE.2013.1252","DOIUrl":"https://doi.org/10.1166/JOLPE.2013.1252","url":null,"abstract":"","PeriodicalId":43794,"journal":{"name":"Journal of Low Power Electronics","volume":"9 1","pages":"221-228"},"PeriodicalIF":0.0,"publicationDate":"2013-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64643151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Circuit-Level Modeling of SRAM Minimum Operating Voltage Vddmin in the C40 Node C40节点SRAM最小工作电压Vddmin的电路级建模
Journal of Low Power Electronics Pub Date : 2012-02-01 DOI: 10.1166/JOLPE.2012.1176
L. Ciampolini, Siddharth Gupta, O. Callen, A. Chhabra, Dibya Dipti, S. Haendler, Shishir Kumar, D. Noblet, P. Malinge, N. Planes, D. Turgis, C. Lecocq, Shamsi Azmi
{"title":"Circuit-Level Modeling of SRAM Minimum Operating Voltage Vddmin in the C40 Node","authors":"L. Ciampolini, Siddharth Gupta, O. Callen, A. Chhabra, Dibya Dipti, S. Haendler, Shishir Kumar, D. Noblet, P. Malinge, N. Planes, D. Turgis, C. Lecocq, Shamsi Azmi","doi":"10.1166/JOLPE.2012.1176","DOIUrl":"https://doi.org/10.1166/JOLPE.2012.1176","url":null,"abstract":"","PeriodicalId":43794,"journal":{"name":"Journal of Low Power Electronics","volume":"8 1","pages":"106-112"},"PeriodicalIF":0.0,"publicationDate":"2012-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64643105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Leakage and Leakage Sensitivity Computation for Combinational Circuits 组合电路的泄漏和泄漏灵敏度计算
Journal of Low Power Electronics Pub Date : 2005-08-01 DOI: 10.1166/jolpe.2005.026
E. Acar, A. Devgan, S. Nassif
{"title":"Leakage and Leakage Sensitivity Computation for Combinational Circuits","authors":"E. Acar, A. Devgan, S. Nassif","doi":"10.1166/jolpe.2005.026","DOIUrl":"https://doi.org/10.1166/jolpe.2005.026","url":null,"abstract":"","PeriodicalId":43794,"journal":{"name":"Journal of Low Power Electronics","volume":"1 1","pages":"172-181"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64643074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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