{"title":"On-Chip Networks for Multicore Systems","authors":"L. Peh, S. Keckler, S. Vangal","doi":"10.1007/978-1-4419-0263-4_2","DOIUrl":"https://doi.org/10.1007/978-1-4419-0263-4_2","url":null,"abstract":"","PeriodicalId":436226,"journal":{"name":"Multicore Processors and Systems","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123486729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Taylor, Walter Lee, Jason E. Miller, D. Wentzlaff, Ian Bratt, B. Greenwald, H. Hoffmann, Paul R. Johnson, J. Kim, James Psota, A. Saraf, N. Shnidman, V. Strumpen, M. Frank, Saman P. Amarasinghe, A. Agarwal
{"title":"Tiled Multicore Processors","authors":"M. Taylor, Walter Lee, Jason E. Miller, D. Wentzlaff, Ian Bratt, B. Greenwald, H. Hoffmann, Paul R. Johnson, J. Kim, James Psota, A. Saraf, N. Shnidman, V. Strumpen, M. Frank, Saman P. Amarasinghe, A. Agarwal","doi":"10.1007/978-1-4419-0263-4_1","DOIUrl":"https://doi.org/10.1007/978-1-4419-0263-4_1","url":null,"abstract":"","PeriodicalId":436226,"journal":{"name":"Multicore Processors and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127275968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Throughput-Oriented Multicore Processors","authors":"J. Laudon, R. Golla, G. Grohoski","doi":"10.1007/978-1-4419-0263-4_7","DOIUrl":"https://doi.org/10.1007/978-1-4419-0263-4_7","url":null,"abstract":"","PeriodicalId":436226,"journal":{"name":"Multicore Processors and Systems","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130971302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Heterogeneous Multi-core Processors: The Cell Broadband Engine","authors":"H. P. Hofstee","doi":"10.1007/978-1-4419-0263-4_9","DOIUrl":"https://doi.org/10.1007/978-1-4419-0263-4_9","url":null,"abstract":"","PeriodicalId":436226,"journal":{"name":"Multicore Processors and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123743631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Composable Multicore Chips","authors":"D. Burger, S. Keckler, S. Sethumadhavan","doi":"10.1007/978-1-4419-0263-4_3","DOIUrl":"https://doi.org/10.1007/978-1-4419-0263-4_3","url":null,"abstract":"","PeriodicalId":436226,"journal":{"name":"Multicore Processors and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128682581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Stream Processors","authors":"M. Erez, W. Dally","doi":"10.1007/978-1-4419-0263-4_8","DOIUrl":"https://doi.org/10.1007/978-1-4419-0263-4_8","url":null,"abstract":"","PeriodicalId":436226,"journal":{"name":"Multicore Processors and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122548628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Speculatively Multithreaded Architectures","authors":"G. Sohi, T. N. Vijaykumar","doi":"10.1007/978-1-4419-0263-4_4","DOIUrl":"https://doi.org/10.1007/978-1-4419-0263-4_4","url":null,"abstract":"","PeriodicalId":436226,"journal":{"name":"Multicore Processors and Systems","volume":"339 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115672206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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