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Accelerating differential power analysis on heterogeneous systems 加速异构系统的差分功率分析
WESS '14 Pub Date : 2014-10-12 DOI: 10.1145/2668322.2668326
J. Amaral, F. Regazzoni, P. Tomás, R. Chaves
{"title":"Accelerating differential power analysis on heterogeneous systems","authors":"J. Amaral, F. Regazzoni, P. Tomás, R. Chaves","doi":"10.1145/2668322.2668326","DOIUrl":"https://doi.org/10.1145/2668322.2668326","url":null,"abstract":"Differential Power Analysis (DPA) attacks allows discovering the secret key stored into secure embedded systems by exploiting the correlation between the power consumed by a device and the data being processed. The computation involved is generally relatively simple, however, if the used power traces are composed by a large number of points, the processing time can be long. In this paper we aim at speeding up the so called correlation power analysis (CPA). To do so, we used the OpenCL framework to distribute the workload of the attack over an heterogeneous platform composed by a CPU and multiple accelerators. We concentrate in the computation of the Pearson's correlation coefficients, as they cover approximately 80% of the overall execution time, and we further optimize the attack by minimizing the data transfers between the host processor and the GPUs. Our results show performance improvements of up to 9x when compared with the reference parallel implementation.","PeriodicalId":434126,"journal":{"name":"WESS '14","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128065266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Encoding the state of integrated circuits: a proactive and reactive protection against hardware Trojans horses 编码集成电路的状态:一种针对硬件木马的主动和被动保护
WESS '14 Pub Date : 2014-10-12 DOI: 10.1145/2668322.2668329
X. Ngo, S. Guilley, S. Bhasin, J. Danger, Zakaria Najm
{"title":"Encoding the state of integrated circuits: a proactive and reactive protection against hardware Trojans horses","authors":"X. Ngo, S. Guilley, S. Bhasin, J. Danger, Zakaria Najm","doi":"10.1145/2668322.2668329","DOIUrl":"https://doi.org/10.1145/2668322.2668329","url":null,"abstract":"Hardware Trojan Horses (HTH) are a serious threat to semiconductor industry with significant economic impact. However, most of the research in HTH focuses on detection. We propose the concept of \"encoded circuit\", as a technique to protect HTH insertion. Encoded circuit is based on the theory of codes. It encodes the internal state with a chosen code of security parameter d, such that knowledge of less than d bits of the encoded state reveals no information about the actual state. This parameter stems from a similar notion introduced by Ishai, Sahai and Wagner at CRYPTO 2003 for the prevention of probing attacks. Usually d < 10 in probing attacks, whereas HTH are able to connect to more than 10 nets. In this paper, we discuss the theory behind \"encoded circuits\" and its practical demonstration on various HDL circuits.","PeriodicalId":434126,"journal":{"name":"WESS '14","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121527027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Detection, traceback and filtering of denial of service attacks in networked embedded systems 网络嵌入式系统中拒绝服务攻击的检测、回溯与过滤
WESS '14 Pub Date : 2014-10-12 DOI: 10.1145/2668322.2668327
A. Papalambrou, K. Stefanidis, J. Gialelis, D. Serpanos
{"title":"Detection, traceback and filtering of denial of service attacks in networked embedded systems","authors":"A. Papalambrou, K. Stefanidis, J. Gialelis, D. Serpanos","doi":"10.1145/2668322.2668327","DOIUrl":"https://doi.org/10.1145/2668322.2668327","url":null,"abstract":"This work presents a composite scheme for detection, traceback and filtering of distributed denial of service (DDoS) attacks in networked embedded systems. A method based on algorithmic analysis of various node and network parameters is used to detect attacks while a packet marking method is used to mitigate the effects of the attack by filtering the incoming traffic that is part of this attack and trace back to the origin of the attack. The combination of the detection and mitigation methods provide an increased level of security in comparison to approaches based on a single method. Furthermore, the scheme is developed in a way to comply with the novel SHIELD secure architecture being developed, which aims at providing interoperability with other secure components as well as metrics to quantify their security properties.","PeriodicalId":434126,"journal":{"name":"WESS '14","volume":"262 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122929544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Information theoretic models for signatures in VLSI power delivery systems 超大规模集成电路电力传输系统信号的信息理论模型
WESS '14 Pub Date : 2014-10-12 DOI: 10.1145/2668322.2668324
M. Wolf, S. Mukhopadhyay
{"title":"Information theoretic models for signatures in VLSI power delivery systems","authors":"M. Wolf, S. Mukhopadhyay","doi":"10.1145/2668322.2668324","DOIUrl":"https://doi.org/10.1145/2668322.2668324","url":null,"abstract":"We propose several abstract models for power distribution systems (PDSs) and show how the physics of PDNs pose limits on our ability to protect against power attacks. Integrated circuits increasingly use integrated voltage regulators (IVRs) to condition the on-chip power signal. IVRs present new opportunities for both decreasing observability of logic activity (power attacks) and monitoring the details of logic activity (Trojan horse detection). We propose three different models for the information in regulated power signals. Longer regulation periods improve the regulator's ability to hide information about the behavior of the logic; unfortunately, longer regulation periods may result in poorer power quality or larger regulator area.","PeriodicalId":434126,"journal":{"name":"WESS '14","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133236607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Trusted sharing of intellectual property in electronic hardware design 电子硬件设计中知识产权的可信共享
WESS '14 Pub Date : 2014-10-12 DOI: 10.1145/2668322.2668331
Debasri Saha, S. Sur-Kolay
{"title":"Trusted sharing of intellectual property in electronic hardware design","authors":"Debasri Saha, S. Sur-Kolay","doi":"10.1145/2668322.2668331","DOIUrl":"https://doi.org/10.1145/2668322.2668331","url":null,"abstract":"In the emerging field of Intellectual property protection and security for ICs and SoCs with design reuse for shorter time-to-market (Fig. 1), misappropriation may be categorized as (i) unauthorized access or interception, (ii) generation of illegal copies and (iii) insertion of hardware trojan horse (Fig. 2).","PeriodicalId":434126,"journal":{"name":"WESS '14","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115525397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet 利用FPGA在以太网上的动态部分重构，通过硬件木马插入对AES进行故障攻击
WESS '14 Pub Date : 2014-10-12 DOI: 10.1145/2668322.2668323
Anju P. Johnson, Sayandeep Saha, R. Chakraborty, Debdeep Mukhopadhyay, Sezer Gören
{"title":"Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet","authors":"Anju P. Johnson, Sayandeep Saha, R. Chakraborty, Debdeep Mukhopadhyay, Sezer Gören","doi":"10.1145/2668322.2668323","DOIUrl":"https://doi.org/10.1145/2668322.2668323","url":null,"abstract":"We describe a novel methodology to exploit the widely used Dynamic Partial Reconfiguration (DPR) support in Field Programmable Gate Arrays (FPGAs) to implant a hardware Trojan in an Advanced Encryption Standard (AES) encryption circuit implemented on a FPGA. The DPR is performed by transferring the required partial configuration bitstream file over an Ethernet connection to the FPGA board, from an attacker's computer which can communicate with the FPGA over a network. The inserted Trojan launches a \"fault attack\" on the AES encryption circuit, which enables recovery of the secret key by standard mathematical analysis of the faulty ciphertext produced. To the best of our knowledge, this is the first reported attack which exploits DPR to break an AES hardware implementation on FPGA. Our implementation results establish this to be an extremely potent attack on AES at low hardware and computational overhead, while using the standard unlicensed FPGA design tools.","PeriodicalId":434126,"journal":{"name":"WESS '14","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127291362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Risk management in embedded devices using metering applications as example 以计量应用程序为例的嵌入式设备风险管理
WESS '14 Pub Date : 2014-10-12 DOI: 10.1145/2668322.2668328
O. Guillen, R. Brederlow, Ralph Ledwa, G. Sigl
{"title":"Risk management in embedded devices using metering applications as example","authors":"O. Guillen, R. Brederlow, Ralph Ledwa, G. Sigl","doi":"10.1145/2668322.2668328","DOIUrl":"https://doi.org/10.1145/2668322.2668328","url":null,"abstract":"Along with the rise in use of everyday life electronic products that collect and communicate personal data, there is an increasing need for adequate security. The use of ultra-low-power MCUs in such applications provides a clear advantage in terms of energy consumption. However, given their general-purpose nature and low-power needs, security has not been the main focus in the past. This work places emphasis on methodologically analyzing open security gaps at a system level and providing a score for each vulnerability found. Such vulnerability scores help prioritize the efforts towards building a secure system and balancing the trade-off between suitable protection and minimal cost. The work presented uses as an example an abstraction of metering applications implemented using a general purpose microcontroller. The presented approach makes use of the Common Vulnerability Scoring System open framework to quantify the impact of possible vulnerabilities and prioritize their remediation based on their relevancy.","PeriodicalId":434126,"journal":{"name":"WESS '14","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133964466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Some RSSB constructions with improved resistance towards differential power analysis 一些抗差分功率分析的RSSB结构
WESS '14 Pub Date : 2014-10-12 DOI: 10.1145/2668322.2668330
Bodhisatwa Mazumdar
{"title":"Some RSSB constructions with improved resistance towards differential power analysis","authors":"Bodhisatwa Mazumdar","doi":"10.1145/2668322.2668330","DOIUrl":"https://doi.org/10.1145/2668322.2668330","url":null,"abstract":"In 1999, Kocher et al. demonstrated the differential power analysis (DPA) attacks on secured cryptographic implementation of AES. Later, this attack along with correlation power analysis (CPA) posed a critical challenge from cryptographers' perspective that not only mathematical security of a cryptographic algorithm, the physical security of its implementation (be it software or hardware) must be proven to call the system \"secured\".\u0000 The class of rotation symmetric S-boxes (RSSBs) are linearly equivalent to the S-boxes constructed from power maps which means the important crytographic properties of the power maps are also present in the class of RSSBs. In this talk, we present some RSSB constructions which are targeted for improved resistance to DPA attacks and also have a good tradeoff of cryptographic properties like high nonlinearity and low GAC absolute indicator value.","PeriodicalId":434126,"journal":{"name":"WESS '14","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124518594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A signature based architecture for Trojan detection 基于签名的木马检测体系结构
WESS '14 Pub Date : 2014-10-12 DOI: 10.1145/2668322.2668325
Aderinola Gbade-Alabi, D. Keezer, V. Mooney, A. Poschmann, Marc Stöttinger, Kshitij Divekar
{"title":"A signature based architecture for Trojan detection","authors":"Aderinola Gbade-Alabi, D. Keezer, V. Mooney, A. Poschmann, Marc Stöttinger, Kshitij Divekar","doi":"10.1145/2668322.2668325","DOIUrl":"https://doi.org/10.1145/2668322.2668325","url":null,"abstract":"Trust in the integrated circuit (IC) fabrication industry is an ongoing concern given the trend towards \"fabless\" design and associated use of third-parties for fabrication. A Hardware Trojan (HT) introduced during fabrication can corrupt an IC's outputs, leak secret information, and yet go undetected by traditional system testing techniques. In this paper we propose an architecture to detect HTs during IC test or at run-time. An HT that would corrupt an IC's output and otherwise proceed undetected will then be rendered useless by this architecture. This approach will therefore discourage the insertion of HTs in the first place. The proposed architecture takes encryption hardware as a paradigmatic case-study and uses digital \"signatures\" derived from the plaintext to identify if the ciphertext has been corrupted by HTs. We test this methodology through simulation on various types of HTs inserted into a lightweight cryptographic system called \"PRESENT\"[13]. Our results validate that activated HTs are detected by this methodology.","PeriodicalId":434126,"journal":{"name":"WESS '14","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128994115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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