2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)最新文献

Power line communication for hybrid power/signal pin SOC design 电力线通信的混合电源/信号引脚SOC设计

2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2015-06-06 DOI: 10.1109/SLIP.2015.7171711

Xiang Zhang, Yang Liu, R. Coutts, Chung-Kuan Cheng

引用次数: 1

On fast timing closure: speeding up incremental path-based timing analysis with mapreduce 关于快速时序关闭:使用mapreduce加速增量路径时序分析

2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2015-06-06 DOI: 10.1109/SLIP.2015.7171710

Tsung-Wei Huang, Martin D. F. Wong

引用次数: 3

Lynx: a self-organizing wireless sensor network with commodity palmtop computers Lynx:一种自组织无线传感器网络，使用普通掌上电脑

2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2015-06-06 DOI: 10.1109/SLIP.2015.7171712

Haifeng Xu, M. Bilec, William O. Collinge, L. Schaefer, A. Landis, A. Jones

{"title":"Lynx: a self-organizing wireless sensor network with commodity palmtop computers","authors":"Haifeng Xu, M. Bilec, William O. Collinge, L. Schaefer, A. Landis, A. Jones","doi":"10.1109/SLIP.2015.7171712","DOIUrl":"https://doi.org/10.1109/SLIP.2015.7171712","url":null,"abstract":"While the embedded class processors found in commodity palmtop computers continue to become increasingly capable, various wireless connectivity functions on them provide new opportunities in designing more flexible yet smarter wireless sensor networks (WSNs), and utilizing the computation power in a way we could never imagine before. Designing Lynx, a selforganizing wireless sensor network (SOWSN), is our further step taken in exploiting the potential of palmtop computers. Fundamental functionalities such as automatic neighbor relation detection, link state maintenance, sensor integration, and multihop routing, together make a real world distributively managed WSN system implementation work quite well. And by combining with Ocelot, our mobile distributed computing engine, sensor nodes are now capable of collecting, recording, processing and sending data without any central server support. Significant energy saving is achieved by the Lynx and Ocelot combined system, compare to traditional power-hungry computer platforms such as BOINC when doing same tasks.","PeriodicalId":431489,"journal":{"name":"2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130350229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Smart I/Os: a data-pattern aware 2.5D interconnect with space-time multiplexing 智能I/ o:一种数据模式感知的2.5D时空复用互连

2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2015-06-06 DOI: 10.1109/SLIP.2015.7171707

Sai Manoj Pudukotai Dinakarrao, Kanwen Wang, Hantao Huang, Hao Yu

引用次数: 2

Multi-product floorplan and uncore design framework for chip multiprocessors 芯片多处理器的多产品平面图和非核心设计框架

2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2015-06-06 DOI: 10.1109/SLIP.2015.7171713

M. Escalante, A. Kahng, M. Kishinevsky, Ümit Y. Ogras, K. Samadi

引用次数: 1

Compact modeling and system implications of microring modulators in nanophotonic interconnects 纳米光子互连中微环调制器的紧凑建模和系统意义

2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2015-06-06 DOI: 10.1109/SLIP.2015.7171708

Rui Wu, Chin-Hui Chen, J. Fédéli, M. Fournier, R. Beausoleil, K. Cheng

引用次数: 15

SI for free: machine learning of interconnect coupling delay and transition effects 免费SI:互连耦合延迟和跃迁效应的机器学习

2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2015-06-06 DOI: 10.1109/SLIP.2015.7171706

A. Kahng, Mulong Luo, S. Nath

{"title":"SI for free: machine learning of interconnect coupling delay and transition effects","authors":"A. Kahng, Mulong Luo, S. Nath","doi":"10.1109/SLIP.2015.7171706","DOIUrl":"https://doi.org/10.1109/SLIP.2015.7171706","url":null,"abstract":"In advanced technology nodes, incremental delay due to coupling is a serious concern. Design companies spend significant resources on static timing analysis (STA) tool licenses with signal integrity (SI) enabled. The runtime of the STA tools in SI mode is typically large due to complex algorithms and iterative calculation of timing windows to accurately determine aggressor and victim alignments, as well as delay and slew estimations. In this work, we develop machine learning-based predictors of timing in SI mode based on timing reports from non-SI mode. Timing analysis in non-SI mode is faster and the license costs can be several times less than those of SI mode. We determine electrical and logic structure parameters that affect the incremental arc delay/slew and path delay (i.e., the difference in arrival times at the clock pin of the launch flip-flop and the D pin of the capture flip-flop) in SI mode, and develop models that can predict these SI-aware delays. We report worst-case error of 7.0ps and average error of 0.7ps for our models to predict incremental transition time, worst-case error of 5.2ps and average error of 1.2ps for our models to predict incremental delay, and worst-case error of 8.2ps and average error of 1.7ps for our models to predict path delay, in 28nm FDSOI technology. We also demonstrate that our models are robust across designs and signoff constraints at a particular technology node.","PeriodicalId":431489,"journal":{"name":"2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128071679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 41

Clock clustering and IO optimization for 3D integration 时钟集群和IO优化的3D集成

2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2015-06-06 DOI: 10.1109/SLIP.2015.7171709

Samyoung Bang, Kwangsoo Han, A. Kahng, V. Srinivas

引用次数: 2