International Workshop on Security Proofs for Embedded Systems最新文献

Constructing Sliding Windows Leak from Noisy Cache Timing Information of OSS-RSA 基于噪声的OSS-RSA缓存时间信息构造滑动窗泄漏

International Workshop on Security Proofs for Embedded Systems Pub Date : 2019-09-06 DOI: 10.29007/ws8z

Rei Ueno, J. Takahashi, Yu-ichi Hayashi, N. Homma

引用次数: 2

Rock'n'roll PUFs: Crafting Provably Secure PUFs from Less Secure Ones 摇滚PUFs:从不太安全的PUFs中制作可证明安全的PUFs

International Workshop on Security Proofs for Embedded Systems Pub Date : 2019-09-06 DOI: 10.29007/nbm3

F. Ganji, Shahin Tajik, Pascal Stauss, Jean-Pierre Seifert, Domenic Forte, M. Tehranipoor

引用次数: 9

Detection and Correction of Malicious and Natural Faults in Cryptographic Modules 密码模块中恶意和自然故障的检测与纠正

International Workshop on Security Proofs for Embedded Systems Pub Date : 2018-09-10 DOI: 10.29007/w37p

Batya Karp, Mael Gay, O. Keren, I. Polian

引用次数: 9

A Non-Reversible Insertion Method for Hardware Trojans Based on Path Delay Faults 一种基于路径延迟故障的硬件木马不可逆插入方法

International Workshop on Security Proofs for Embedded Systems Pub Date : 2018-09-10 DOI: 10.29007/fxvv

Akira Ito, Rei Ueno, N. Homma, T. Aoki

{"title":"A Non-Reversible Insertion Method for Hardware Trojans Based on Path Delay Faults","authors":"Akira Ito, Rei Ueno, N. Homma, T. Aoki","doi":"10.29007/fxvv","DOIUrl":"https://doi.org/10.29007/fxvv","url":null,"abstract":"This paper presents a non-reversible method for stealthily inserting hardware Trojan (HT) based on a path delay fault called Path Delay HT (PDHT). While PDHT is hardly detected by the conventional methods including Monte-Carlo tests, its practicality is still unclear because a rarely sensitized path used for PDHT is selected and exploited in a deterministic manner. Such deterministic method indicates that we can find possible PDHT-inserted paths by its reversed method. In addition, the conventional method uses a genetic algorithm to add extra delays onto the selected path for inducing a path delay fault, and therefore, we have a difficulty in evaluating the resistance/vulnerability of a circuit to PDHT. This paper first presents a new method for selecting sufficiently rare paths to insert PDHT at random. We then show that the detectability/stealthiness of PDHT is related to switching activity (i.e., glitch effect), and present a new systematic method for inducing a path delay fault instead of GA. We demonstrate through an experimental PDHT-insertion and a Monte-Carlo test that the PDHT inserted by our method is sufficiently undetectable in comparison with the conventional method.","PeriodicalId":398629,"journal":{"name":"International Workshop on Security Proofs for Embedded Systems","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134132590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Side-Channel Assisted Malware Classifier with Gradient Descent Correction for Embedded Platforms 基于梯度下降校正的嵌入式平台侧信道辅助恶意分类器

International Workshop on Security Proofs for Embedded Systems Pub Date : 2018-09-10 DOI: 10.29007/5sdj

Manaar Alam, Debdeep Mukhopadhyay, S. Kadiyala, S. Lam, T. Srikanthan

{"title":"Side-Channel Assisted Malware Classifier with Gradient Descent Correction for Embedded Platforms","authors":"Manaar Alam, Debdeep Mukhopadhyay, S. Kadiyala, S. Lam, T. Srikanthan","doi":"10.29007/5sdj","DOIUrl":"https://doi.org/10.29007/5sdj","url":null,"abstract":"Malware detection is still one of the difficult problems in computer security because of the occurrence of newer varieties of malware programs. There has been an enormous effort in developing a generalised solution to this problem, but a little has been done considering the security of resource constraint embedded devices. In this paper, we attempt to develop a lightweight malware detection tool designed specifically for embedded platforms using micro-architectural side-channel information obtained through Hardware Performance Counters (HPCs). The methodology aims to develop a distance metric, called λ, for a given program from a benign set of programs which are expected to execute in the embedded environment. The distance metric is decided based on observations from carefully chosen features, which are tuples of high-level system calls along with low-level HPC events. An ideal λ-value for a malicious program is 1, as opposed to 0 for a benign program. However, in reality, the efficacy of λ to classify a malware largely depends on the proper assignment of weights to the features. We employ a gradient-descent based learning mechanism to determine optimal choices for these weights. We justify through experimental results on an embedded Linux running on an ARM processor that such a side-channel based learning mechanism improves the classification accuracy significantly compared to an ad-hoc selection of the weights, and leads to significantly low false positives and false negatives in all our test cases.","PeriodicalId":398629,"journal":{"name":"International Workshop on Security Proofs for Embedded Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125141033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Attack-tree-based Threat Modeling of Medical Implants 基于攻击树的医疗植入物威胁建模

International Workshop on Security Proofs for Embedded Systems Pub Date : 2018-09-10 DOI: 10.29007/8gxh

M. Siddiqi, R. M. Seepers, Mohammad Hamad, V. Prevelakis, C. Strydis

引用次数: 18

An Automated Framework for Exploitable Fault Identification in Block Ciphers - A Data Mining Approach 块密码中可利用故障识别的自动框架——一种数据挖掘方法

International Workshop on Security Proofs for Embedded Systems Pub Date : 2017-10-04 DOI: 10.29007/fmzl

Sayandeep Saha, Ujjawal Kumar, Debdeep Mukhopadhyay, P. Dasgupta

{"title":"An Automated Framework for Exploitable Fault Identification in Block Ciphers - A Data Mining Approach","authors":"Sayandeep Saha, Ujjawal Kumar, Debdeep Mukhopadhyay, P. Dasgupta","doi":"10.29007/fmzl","DOIUrl":"https://doi.org/10.29007/fmzl","url":null,"abstract":"Characterization of all possible faults in a cryptosystem exploitable for fault attacks is a problem which is of both theoretical and practical interest for the cryptographic community. The complete knowledge of exploitable fault space is desirable while designing optimal countermeasures for any given crypto-implementation. In this paper, we address the exploitable fault characterization problem in the context of Differential Fault Analysis (DFA) attacks on block ciphers. The formidable size of the fault spaces demands an automated albeit fast mechanism for verifying each individual fault instance and neither the traditional, cipher-specific, manual DFA techniques nor the generic and automated Algebraic Fault Attacks (AFA) [10] fulfill these criteria. Further, the diversified structures of different block ciphers suggest that such an automation should be equally applicable to any block cipher. This work presents an automated framework for DFA identification, fulfilling all aforementioned criteria, which, instead of performing the attack just estimates the attack complexity for each individual fault instance. A generic and extendable data-mining assisted dynamic analysis framework capable of capturing a large class of DFA distinguishers is devised, along with a graph-based complexity analysis scheme. The framework significantly outperforms another recently proposed one [6], in terms of attack class coverage and automation effort. Experimental evaluation on AES and PRESENT establishes the effectiveness of the proposed framework in detecting most of the known DFAs, which eventually enables the characterization of the exploitable fault space.","PeriodicalId":398629,"journal":{"name":"International Workshop on Security Proofs for Embedded Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127178321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Symbolic Approach for Side-Channel Resistance Analysis of Masked Assembly Codes 屏蔽组合码侧信道电阻分析的符号方法

International Workshop on Security Proofs for Embedded Systems Pub Date : 2017-10-04 DOI: 10.29007/hhnf

Inès Ben El Ouahma, Quentin L. Meunier, K. Heydemann, Emmanuelle Encrenaz-Tiphène

引用次数: 17