Proceedings of the Third ACM International Workshop on Many-core Embedded Systems最新文献

{"title":"Highly Concurrent Stream Synchronization in Many-core Embedded Systems","authors":"Y. Nikolakopoulos, M. Papatriantafilou, P. Brauer, Martin Lundqvist, Vincenzo Gulisano, P. Tsigas","doi":"10.1145/2934495.2934496","DOIUrl":"https://doi.org/10.1145/2934495.2934496","url":null,"abstract":"Embedded many-core architectures are expected to serve as significant components in the infrastructure of upcoming technologies like networks for the Internet of Things (IoT), facing real-time and stream processing challenges. In this work we explore the applicability of ScaleGate, a synchronization object from the massive data stream processing domain, on many-core embedded systems. We propose a new implementation of ScaleGate on the Epiphany architecture, a scalable embedded many-core co-processor, and study communication patterns that appear in the context of a baseband signal processing application. Our experimental evaluation shows significant improvements over standard barrier-based approaches, due to the asynchrony exploited by the use of ScaleGate.","PeriodicalId":383106,"journal":{"name":"Proceedings of the Third ACM International Workshop on Many-core Embedded Systems","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117199938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dataflow Implementation of QR Decomposition on a Manycore","authors":"Süleyman Savas, Sebastian Raase, Essayas Gebrewahid, Z. Ul-Abdin, T. Nordström","doi":"10.1145/2934495.2934499","DOIUrl":"https://doi.org/10.1145/2934495.2934499","url":null,"abstract":"While parallel computer architectures have become mainstream, application development on them is still challenging. There is a need for new tools, languages and programming models. Additionally, there is a lack of knowledge about the performance of parallel approaches of basic but important operations, such as the QR decomposition of a matrix, on current commercial manycore architectures. This paper evaluates a high level dataflow language (CAL), a source-to-source compiler (Cal2Many) and three QR decomposition algorithms (Givens Rotations, Householder and Gram-Schmidt). The algorithms are implemented both in CAL and hand-optimized C languages, executed on Adapteva's Epiphany manycore architecture and evaluated with respect to performance, scalability and development effort. The performance of the CAL (generated C) implementations gets as good as 2% slower than the hand-written versions. They require an average of 25% fewer lines of source code without significantly increasing the binary size. Development effort is reduced and debugging is significantly simplified. The implementations executed on Epiphany cores outperform the GNU scientific library on the host ARM processor of the Parallella board by up to 30x.","PeriodicalId":383106,"journal":{"name":"Proceedings of the Third ACM International Workshop on Many-core Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120969044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The SiLago Method: Next Generation VLSI Architectures and Design Methods","authors":"A. Hemani","doi":"10.1145/2934495.2936779","DOIUrl":"https://doi.org/10.1145/2934495.2936779","url":null,"abstract":"ions has forced the community to adopt software centric accelerator rich platform based design style. This design style delivers poor silicon and computational efficiencies and typically only customizes computational aspects of functionality that is power and performance critical. As a solution, we propose raising the physical design platform from present day boolean level to micro-architectural level by proposing micro-architecture level SiLago (Silicon Large Grain Objects) blocks as the atomic physical design building blocks and introduce a grid based structured layout scheme as a new physical design discipline to compose an arbitrary design by simply abutting SiLago blocks and eliminating the logic and physical synthesis. We call this the SiLago method and show that it provides 2-3 orders more efficient synthesis from application level compared to the standard cell based commercial design flows with a modest loss in design quality. The SiLago method not only reduces the VLSI engineering cost, but it also holds promise to significantly reduce the cost of making masks that is one of the most expensive NRE costs in manufacturing. The cost of making masks can be lowered because in the SiLago method, the mask becomes composable in terms of the component SiLago block masks. As there are finite number of SiLago block types that can have only a finite number of neighbor SiLago block types, it is possible to store as pre-determined patterns of the SiLago block types in a library that are corrected for all types of lithographic impairments. A mask for any arbitrary SiLago design can be generated by composing in terms of the component masks of the SiLago block types and the types of neighboring SiLago blocks. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. MES ’16, June 19 2016, Seoul, Republic of Korea c 2016 Copyright held by the owner/author(s). Publication rights licensed to ACM. ISBN 978-1-4503-4262-9/16/06. . . $15.00 DOI: http://dx.doi.org/10.1145/2934495.2936779","PeriodicalId":383106,"journal":{"name":"Proceedings of the Third ACM International Workshop on Many-core Embedded Systems","volume":"429 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132334870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Vector Processors for Energy-Efficient Embedded Systems","authors":"D. Dabbelt, Colin Schmidt, Eric Love, Howard Mao, S. Karandikar, K. Asanović","doi":"10.1145/2934495.2934497","DOIUrl":"https://doi.org/10.1145/2934495.2934497","url":null,"abstract":"High-performance embedded processors are frequently designed as arrays of small, in-order scalar cores, even when their workloads exhibit high degrees of data-level parallelism (DLP). We show that these multiple instruction, multiple data (MIMD) systems can be made more efficient by instead directly exploiting DLP using a modern vector architecture. In our study, we compare arrays of scalar cores to vector machines of comparable silicon area and power consumption. Since vectors provide greater performance across the board - in some cases even with better programmability - we believe that embedded system designers should increasingly pursue vector architectures for machines at this scale.","PeriodicalId":383106,"journal":{"name":"Proceedings of the Third ACM International Workshop on Many-core Embedded Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127333528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping","authors":"Junshi Wang, Yang Huang, M. Ebrahimi, Letian Huang, Qiang Li, A. Jantsch, Guangjun Li","doi":"10.1145/2934495.2949544","DOIUrl":"https://doi.org/10.1145/2934495.2949544","url":null,"abstract":"Simulation is the most common approach to evaluate Network on Chip (NoC) designs and many simulators at different abstraction levels have been developed so far. However, researchers have to spend a considerable amount of time and effort to debug, analyze, and extract meaningful information from the simulator reports. In this work, we propose a full-system visualization framework, called VisualNoC, that support both network simulation and task mapping. VisualNoC operates in a cycle-accurate mode and is based on an event-based trace model which can record the behaviors of routers, processing elements and packets. The visualization interface can provide efficient debugging and analysis platform by representing the simulation process and results in a variety of ways. One of the main features of VisualNoC is providing an intuitive way of analyzing the efficiency of different mapping algorithms that helps in finding bottlenecks and optimizing the design.","PeriodicalId":383106,"journal":{"name":"Proceedings of the Third ACM International Workshop on Many-core Embedded Systems","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121637509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}