Design-Process-Technology Co-optimization for Manufacturability XIII最新文献

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Design-Process-Technology Co-optimization for Manufacturability XIII Pub Date : 2019-06-14 DOI: 10.1117/12.2533864

引用次数: 0

Pattern-aware diagnostics: using high-performance pattern analysis to identify defect root cause (Conference Presentation) 模式感知诊断:使用高性能模式分析来识别缺陷的根本原因(会议介绍)

Design-Process-Technology Co-optimization for Manufacturability XIII Pub Date : 2019-03-18 DOI: 10.1117/12.2516571

J. Cain, A. Yassine, M. Fakhry, P. Pathak, J. E. Nelson, Frank Gennari, Ya-Chieh Lai

{"title":"Pattern-aware diagnostics: using high-performance pattern analysis to identify defect root cause (Conference Presentation)","authors":"J. Cain, A. Yassine, M. Fakhry, P. Pathak, J. E. Nelson, Frank Gennari, Ya-Chieh Lai","doi":"10.1117/12.2516571","DOIUrl":"https://doi.org/10.1117/12.2516571","url":null,"abstract":"Layout-pattern-based approaches for physical design analysis and verification have become mainstream in recent years and are enabling many new applications. Prior work introduced the ability to collect all patterns from multiple layouts into a catalog as well as to use machine learning techniques to score and filter patterns to identify which ones are critical. In this paper, data mined from a library of scored patterns from established designs is applied to the analysis of diagnosis results from a new design to improve defect root cause analysis (RCA). \u0000The flow for this approach is as follows: patterns interacting with nets reported in diagnosis callouts are selected as patterns of interest (POIs) from the catalog of all patterns. Next, features of interest (FOIs) are extracted from all POIs to build a dataframe. Finally, volume diagnosis results identifying nets with likely open or short defects are added to the dataframe. RCA is performed using the dataframe to identify likely root cause(s) for failures and suggest refined failure locations for targeted inspection, physical failure analysis, or other electrical failure analysis.\u0000The approach described above is applied to products in high-volume manufacturing using a leading-edge technology node. Silicon validation results will be included for example applications.","PeriodicalId":359139,"journal":{"name":"Design-Process-Technology Co-optimization for Manufacturability XIII","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127741093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Applications of machine learning in EDA (Conference Presentation) 机器学习在EDA中的应用(会议报告)

Design-Process-Technology Co-optimization for Manufacturability XIII Pub Date : 2019-03-18 DOI: 10.1117/12.2515268

P. Franzon

{"title":"Applications of machine learning in EDA (Conference Presentation)","authors":"P. Franzon","doi":"10.1117/12.2515268","DOIUrl":"https://doi.org/10.1117/12.2515268","url":null,"abstract":"Machine learning has significant potential to help the human designer produce better outcomes. It can also help manage some of the complexity with chip design in advanced nodes. Projects to be discussed include the following.\u0000o Using Bayesian optimization for circuit IP reuse. Analog and custom digital IP reuse is difficult and time-consuming. Professor Franzon's group has built a Bayesian optimization approach involving statistical surrogate models. They have demonstrated by porting a number of designs between nodes, including a BJT to SOI port. The machine learning based approach produced better results than a human designer.\u0000o Using Surrogate modeling for Physical design. Professor Franzon's group has used a machine learning approach to predict Global Router and detailed router results as a function of tool input settings. These models can be used to tune the tool setup for specific outcomes.\u0000o Using Surrogate Modeling and System Identification Modeling to model digital receiver chains. Digital receiver modeling is predict BER of a receiver in the presence of an input signal with a close eye. Professor Franzon's group has used a combination of Surrogate Modeling and System Identification to build such a modeling capability.\u0000o Using deep networks for design rule checking. The team has demonstrated that deep networks can be used instead of Boolen checkers. There is significant potential to close the DFM and custom design productivity gaps.","PeriodicalId":359139,"journal":{"name":"Design-Process-Technology Co-optimization for Manufacturability XIII","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125865440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0