2020 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)最新文献

Global Interconnects in VLSI Complexity Single Flux Quantum Systems VLSI复杂单通量量子系统中的全局互连

2020 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2020-11-05 DOI: 10.1145/3414622.3431911

T. Jabbari, E. Friedman

{"title":"Global Interconnects in VLSI Complexity Single Flux Quantum Systems","authors":"T. Jabbari, E. Friedman","doi":"10.1145/3414622.3431911","DOIUrl":"https://doi.org/10.1145/3414622.3431911","url":null,"abstract":"On-chip signal routing has become an issue of growing importance in modern VLSI complexity single flux quantum (SFQ) systems. In this paper, different routing methods for these systems are described. The routing methods include either passive transmission lines (PTLs) or Josephson transmission lines (JTLs) as interconnects. Driving multiple SFQ gates is also a challenging issue in automated layout and clock tree synthesis (CTS) due to the limited fanout of SFQ gates. To support multiple fanout, splitters are used to distribute multiple SFQ pulses. These splitters require significant area, delay, and power. In this paper, several area and power efficient splitters are proposed for large scale SFQ integrated circuits. A primary issue within a long SFQ interconnect is resonance effects due to the imperfect match between the PTLs and Josephson junctions. A repeater insertion methodology for long interconnect to reduce and manage these resonance effects is also described. Summarizing, guidelines and tradeoffs appropriate for automated layout and synthesis are described for driving long and short interconnect in VLSI complexity SFQ systems.","PeriodicalId":347769,"journal":{"name":"2020 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126226918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Outlook of device and assembly technologies enabling high-performance mobile computing - IRDS view (Invited) 实现高性能移动计算的设备和装配技术展望- IRDS视图(邀请)

2020 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2020-11-05 DOI: 10.1145/3414622.3431912

M. Badaroglu

引用次数: 0

Optimal Bounded-Skew Steiner Trees to Minimize Maximum k-Active Dynamic Power 最小化最大k-有源动态功率的最优有界偏斯坦纳树

2020 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2020-11-05 DOI: 10.1145/3414622.3431908

H. Fatemi, A. Kahng, Minsoo Kim, J. P. D. Gyvez

{"title":"Optimal Bounded-Skew Steiner Trees to Minimize Maximum k-Active Dynamic Power","authors":"H. Fatemi, A. Kahng, Minsoo Kim, J. P. D. Gyvez","doi":"10.1145/3414622.3431908","DOIUrl":"https://doi.org/10.1145/3414622.3431908","url":null,"abstract":"Static Random-Access Memory (SRAM) is a key component of modern systems-on-chip (SOCs), appearing in on-chip cache memories, FIFOs, and register files. Increasingly, modern SOCs embed more memory hierarchies and various modules which require on-chip memory accesses due to the high cost of off-chip memory accesses, and the lower power density of memory fabrics that helps reduce need for “dark silicon”. For such memory-dominated chips, the product specification and electronic device designers will focus on the maximum power consumption across all power usage scenarios, where a portion of memories are active and others are turned off by clock/power gates. In this work, we introduce and study k-active dynamic power minimization in bounded-skew trees, where we seek to minimize the maximum dynamic power consumption when at most $k$ clock sinks are active. The sizes of SRAM blocks and the SOC die, relative to buffer distances in advanced nodes, effectively linearize clock power and wirelength of clock subtrees. We can therefore apply an extension of a flow-based ILP for bounded-skew Steiner tree construction, introduced at SLIP-2018 [1]. We also introduce and study k-consecutive-active dynamic power minimization in scenarios where only consecutively-indexed clock sinks can be active simultaneously. Further, we demonstrate how non-uniform underlying grids enable the ILP to more flexibly capture locations of terminals of trees. Finally, we study the potential tree cost reduction benefit of flexible clock source locations rather than fixed source locations. Our experimental results give new insight into the tradeoff of maximum k-( consecutive)-active dynamic power and wirelength, and of skew and wirelength.","PeriodicalId":347769,"journal":{"name":"2020 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123653606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Revisiting Inherent Noise Floors for Interconnect Prediction 重新审视互连预测的固有噪声底

2020 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2020-11-05 DOI: 10.1145/3414622.3431907

T. Chan, A. Kahng, M. Woo

{"title":"Revisiting Inherent Noise Floors for Interconnect Prediction","authors":"T. Chan, A. Kahng, M. Woo","doi":"10.1145/3414622.3431907","DOIUrl":"https://doi.org/10.1145/3414622.3431907","url":null,"abstract":"Today's synthesis, placement and routing (SP&R) tools routinely handle millions of instances. Accurate prediction of outcomes is needed to avoid long wasted runtimes from, e.g., unroutable floor-plans or placements. However, tool outputs have inherent noise that implies a lower bound on prediction error [10] [7]. The goal of interconnect prediction naturally raises a question of “How accurate can interconnect prediction be?\" In this work, we revisit the topic of inherent noise and “chaos\" in IC implementation flows, to characterize current noise floors on interconnect prediction. We study effects on commercial P&R tool outcomes of such previously-identified noise sources as reordering and renaming in instance cells, nets, and master cells. We also perform studies for macro placement, by slightly shifting the location of macro placement blockages in the center of the layout floorplan. We find that recent commercial tool versions still show significant routed wirelength noise of up to 7% when netlist reordering is applied, and 11.5% when macro placement blockages are shifted. Finally, we also raise the question of “How should predictions be used?” by showing example scenarios where advance knowledge of physical design outcomes can potentially worsen noise and predictability.","PeriodicalId":347769,"journal":{"name":"2020 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123574572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Pathfinding for 2.5D Interconnect Technologies 2.5D互连技术的寻路

2020 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2020-11-05 DOI: 10.1145/3414622.3431906

Saptadeep Pal, Puneet Gupta

{"title":"Pathfinding for 2.5D Interconnect Technologies","authors":"Saptadeep Pal, Puneet Gupta","doi":"10.1145/3414622.3431906","DOIUrl":"https://doi.org/10.1145/3414622.3431906","url":null,"abstract":"As conventional technology scaling becomes harder, 2.5D integration provides a viable pathway to building larger systems at lower cost. Therefore recently, there has been a proliferation of multiple 2.5D integration technologies that offer different interconnect characteristics such as wiring pitch, bump/pad pitch, inter-die distance, etc. All these factors affect the interconnect metrics of bandwidth, latency and energy-per-bit which ultimately determine system performance. There are other factors such as the choice of ESD circuitry, dicing technology and signaling voltage that also influence these interconnect metrics. In this work, we propose a novel pathfinding methodology for 2.5D interconnect technologies, which seeks to identify the trade-offs among the different factors which affect the performance metrics. We show that incessant scaling of the critical dimensions of the interconnect is not very useful. We emphasize the importance of managing ESD and dicing in improving energy efficiency of these interconnects. We also show that a heterogeneous chiplet ecosystem comes with significant I/O energy penalties. Overall, we demonstrate that a holistic approach considering features of 2.5D integration technology, chiplet technology and various other factors need to be considered and optimized simultaneously to maximize the performance and cost benefits of these integration solutions.","PeriodicalId":347769,"journal":{"name":"2020 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132923664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Building a Quantum Computer (Invited) 构建量子计算机(特邀)

2020 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2020-11-05 DOI: 10.1145/3414622.3431913

B. Sanders

引用次数: 0

Communication Architecture Enabling 100x Accelerated Simulation of Biological Neural Networks 实现100倍加速生物神经网络仿真的通信架构

2020 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2020-11-05 DOI: 10.1145/3414622.3431909

K. Kauth, Tim Stadtmann, Ruben Brandhofer, Vida Sobhani, T. Gemmeke

{"title":"Communication Architecture Enabling 100x Accelerated Simulation of Biological Neural Networks","authors":"K. Kauth, Tim Stadtmann, Ruben Brandhofer, Vida Sobhani, T. Gemmeke","doi":"10.1145/3414622.3431909","DOIUrl":"https://doi.org/10.1145/3414622.3431909","url":null,"abstract":"To further develop the understanding of cognitive processes in the human cortex, neuroscientists seek to simulate relevant biological neural networks in the order of 109 neurons with natural densities of 104 synapses per neuron. To observe long-term effects of learning, a speed-up of at least 100x with respect to biological real-time is required while preserving deterministic results and a high temporal resolution of 0.1 ms. In this paper, we translate these objectives to requirements for the communication architecture of a large-scale neuroscience simulator. These requirements are based on a connectivity model that includes gray and white matter as well as clustered connections and represents essential communication requirements of biological neural networks. In analytical and numerical analysis, existing platforms fall short of meeting all requirements simultaneously even assuming modern high-speed transceivers. This paper presents a balanced multi-hop communication architecture that cuts latency and achieves high bandwidth efficiency. Extrapolating from physical measurements of link performance, our work brings the challenging communication requirements within reach of next generation large-scale neuroscience simulation platforms.","PeriodicalId":347769,"journal":{"name":"2020 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122135721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

3D NoC Emulation Model on a Single FPGA 单FPGA上的三维NoC仿真模型

2020 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2020-11-05 DOI: 10.1145/3414622.3431910

Jonathan D'Hoore, Poona Bahrebar, D. Stroobandt

{"title":"3D NoC Emulation Model on a Single FPGA","authors":"Jonathan D'Hoore, Poona Bahrebar, D. Stroobandt","doi":"10.1145/3414622.3431910","DOIUrl":"https://doi.org/10.1145/3414622.3431910","url":null,"abstract":"Networks-on-Chip (NoCs) have emerged as a promising solution for the communication crisis in large and highly interconnected Systems-on-Chip. To allow investigating path finding solutions for N oC architectures and provide useful insights into the network design aspects, the performance of the designed N oC needs to be evaluated through simulations/emulations. Although software simulators are flexible and can deliver very accurate results, the simulation time is likely to be prohibitive for large-scale designs. Field Programmable Gate Arrays (FPGAs) can speed up the simulation process significantly, while maintaining the same level of accuracy. However, the FPGA-based NoC emulators proposed so far are mostly limited to 2D NoCs. In this paper, we extend the 2D FNoC emulation model to 3D using a single FPGA. The proposed model takes advantage of 3D Time-Division-Multiplexing (TDM) and a clustering method to be able to emulate large (up to 10,648 nodes) N oCs. In order to acquire an estimate of the resource usage on FPGA, a VHDL implementation is developed for certain sub-modules of the emulator. The resulting estimations are used to determine the optimal clustering size. Furthermore, the accuracy of the proposed model is verified against the well-known BookSim simulator.","PeriodicalId":347769,"journal":{"name":"2020 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132729807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1