2020 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC)最新文献

Cache Oblivious Strategies to Exploit Multi-Level Memory on Manycore Systems 利用多核系统多级内存的缓参无关策略

2020 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC) Pub Date : 2020-11-01 DOI: 10.1109/MCHPC51950.2020.00011

Neil A. Butcher, Stephen L. Olivier, P. Kogge

引用次数: 0

Understanding the Impact of Memory Access Patterns in Intel Processors 理解英特尔处理器中内存访问模式的影响

2020 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC) Pub Date : 2020-11-01 DOI: 10.1109/MCHPC51950.2020.00012

Mohammad Alaul Haque Monil, Seyong Lee, J. Vetter, A. Malony

{"title":"Understanding the Impact of Memory Access Patterns in Intel Processors","authors":"Mohammad Alaul Haque Monil, Seyong Lee, J. Vetter, A. Malony","doi":"10.1109/MCHPC51950.2020.00012","DOIUrl":"https://doi.org/10.1109/MCHPC51950.2020.00012","url":null,"abstract":"Because of increasing complexity in the memory hierarchy, predicting the performance of a given application in a given processor is becoming more difficult. The problem is worsened by the fact that the hardware needed to deal with more complex memory traffic also affects energy consumption. Moreover, in a heterogeneous system with shared main memory, the memory traffic between the last level cache (LLC) and the memory creates contention between other processors and accelerator devices. For these reasons, it is important to investigate and understand the impact of different memory access patterns on the memory system. This study investigates the interplay between Intel processors' memory hierarchy and different memory access patterns in applications. The authors explore sequential streaming and strided memory access patterns with the objective of predicting LLC-dynamic random access memory (DRAM) traffic for a given application in given Intel architectures. Moreover, the impact of prefetching is also investigated in this study. Experiments with different Intel micro-architectures uncover mechanisms to predict LLC-DRAM traffic that can yield up to 99% accuracy for sequential streaming access patterns and up to 95% accuracy for strided access patterns.","PeriodicalId":318919,"journal":{"name":"2020 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC)","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132128609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Title Page i 第1页

2020 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC) Pub Date : 2020-11-01 DOI: 10.1109/mchpc51950.2020.00001

引用次数: 0

Performance Potential of Mixed Data Management Modes for Heterogeneous Memory Systems 异构存储系统混合数据管理模式的性能潜力

2020 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC) Pub Date : 2020-11-01 DOI: 10.1109/MCHPC51950.2020.00007

T. Effler, Michael R. Jantz, T. Jones

{"title":"Performance Potential of Mixed Data Management Modes for Heterogeneous Memory Systems","authors":"T. Effler, Michael R. Jantz, T. Jones","doi":"10.1109/MCHPC51950.2020.00007","DOIUrl":"https://doi.org/10.1109/MCHPC51950.2020.00007","url":null,"abstract":"Many high-performance systems now include different types of memory devices within the same compute platform to meet strict performance and cost constraints. Such heterogeneous memory systems often include an upper-level tier with better performance, but limited capacity, and lower-level tiers with higher capacity, but less bandwidth and longer latencies for reads and writes. To utilize the different memory layers efficiently, current systems rely on hardware-directed, memory -side caching or they provide facilities in the operating system (OS) that allow applications to make their own data-tier assignments. Since these data management options each come with their own set of trade-offs, many systems also include mixed data management configurations that allow applications to employ hardware- and software-directed management simultaneously, but for different portions of their address space. Despite the opportunity to address limitations of stand-alone data management options, such mixed management modes are under-utilized in practice, and have not been evaluated in prior studies of complex memory hardware. In this work, we develop custom program profiling, configurations, and policies to study the potential of mixed data management modes to outperform hardware- or software-based management schemes alone. Our experiments, conducted on an Intel ® Knights Landing platform with high-bandwidth memory, demonstrate that the mixed data management mode achieves the same or better performance than the best stand-alone option for five memory intensive benchmark applications (run separately and in isolation), resulting in an average speedup compared to the best stand-alone policy of over 10 %, on average.","PeriodicalId":318919,"journal":{"name":"2020 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115034020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Message from the Workshop Chairs 来自研讨会主席的信息

2020 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC) Pub Date : 2020-11-01 DOI: 10.1109/mchpc51950.2020.00004

Nmic

{"title":"Message from the Workshop Chairs","authors":"Nmic","doi":"10.1109/mchpc51950.2020.00004","DOIUrl":"https://doi.org/10.1109/mchpc51950.2020.00004","url":null,"abstract":"The new computation technologies, such as big data analytics, modern machine learning technology, artificial intelligence (AI), blockchain, and security processing, have the great potential to be embedded into network to enable it to be intelligent and trustworthy. On the other hand, Information-Centric Networking (ICN), software-defined network (SDN), network function virtualization (NFV), Delay Tolerant Network (DTN), Vehicular Ad Hoc NETwork (VANET), network slicing, and data center network have emerged as the novel networking paradigms for fast and efficient delivering and retrieving data. Against this backdrop, there is a strong trend to move the computations from the cloud to not only the edges but also the resource-sufficient networking nodes, which triggers the convergence between the emerging networking concepts and the new computation technologies. The NMIC workshop 2019 brings together researchers to discuss the technical challenges and applications of the distributed computations for networking, the intelligent computations supported by the novel networking technologies, and the enforcement of series of computations. The accepted papers combine the computation technologies with ICN, SDN, DTN, VANET, and mobile network to enable them to be more intelligent, trustworthy, and efficient. We would like to especially thank the ICDCS 2019 organization team and all the TPC members of NMIC workshop 2019. Without their kind help, the NMIC workshop would not be possible.","PeriodicalId":318919,"journal":{"name":"2020 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122434497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Leveraging a Heterogeneous Memory System for a Legacy Fortran Code: The Interplay of Storage Class Memory, DRAM and OS 利用异构内存系统的遗留Fortran代码:存储类内存，DRAM和操作系统的相互作用

2020 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC) Pub Date : 2020-11-01 DOI: 10.1109/MCHPC51950.2020.00008

Steffen Christgau, T. Steinke

引用次数: 2

Architecting Heterogeneous Memory Systems with DRAM Technology Only: A Case Study on Relational Database 仅用DRAM技术构建异构存储系统:以关系数据库为例

2020 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC) Pub Date : 2020-11-01 DOI: 10.1109/MCHPC51950.2020.00009

Yifan Qiao, Xubin Chen, Jingpeng Hao, Tong Zhang, C. Xie, Fei Wu

{"title":"Architecting Heterogeneous Memory Systems with DRAM Technology Only: A Case Study on Relational Database","authors":"Yifan Qiao, Xubin Chen, Jingpeng Hao, Tong Zhang, C. Xie, Fei Wu","doi":"10.1109/MCHPC51950.2020.00009","DOIUrl":"https://doi.org/10.1109/MCHPC51950.2020.00009","url":null,"abstract":"This paper advocates a DRAM-only design strategy to architect high-performance low-cost heterogeneous memory systems in future computing systems, and demonstrates its potential in the context of relational database. In particular, we envision a heterogeneous DRAM fabric consisting of convenient but expensive byte-addressable DRAM and large-capacity low-cost DRAM with coarse access granularity (e.g., 1K-byte). Regardless of specific memory technology, one can reduce the manufacturing cost by sacrificing the memory raw reliability, and apply error correction code (ECC) to restore the data storage integrity. The efficiency of ECC significantly improves as the codeword length increases, which enlarges the memory access granularity. This leads to a fundamental trade-off between memory cost and access granularity. Following this principle, Intel 3DXP-based Optane memory DIMM internally operates with a 256-byte ECC codeword length (hence 256-byte access granularity), and Hynix recently demonstrated low-cost DRAM DIMM with a 64-byte access granularity. This paper presents a design approach that enables relational database to take full advantage of the envisioned low-cost heterogeneous DRAM fabric to improve performance with only minimal database source code modification. Using MySQL as a test vehicle, we implemented a prototyping system, on which we have demonstrated its effectiveness under TPC-C and Sysbench OLTP benchmarks.","PeriodicalId":318919,"journal":{"name":"2020 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129297386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Persistent Memory Object Storage and Indexing for Scientific Computing 用于科学计算的持久内存对象存储和索引

2020 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC) Pub Date : 2020-11-01 DOI: 10.1109/MCHPC51950.2020.00006

Awais Khan, Hyogi Sim, Sudharshan S. Vazhkudai, Jinseok Ma, Myeonghoon Oh, Youngjae Kim

引用次数: 7

Hostile Cache Implications for Small, Dense Linear Solves 小的、密集的线性解的敌对缓存含义

2020 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC) Pub Date : 2020-10-02 DOI: 10.1109/MCHPC51950.2020.00010

Tom Deakin, J. Cownie, Simon McIntosh-Smith, J. Lovegrove, R. Smedley-Stevenson

引用次数: 0