2016 IEEE 34th International Conference on Computer Design (ICCD)最新文献_第10页

SRAM stability analysis for different cache configurations due to Bias Temperature Instability and Hot Carrier Injection 基于偏置温度不稳定性和热载流子注入的SRAM稳定性分析

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753284

Taizhi Liu, Chang-Chih Chen, Jiadong Wu, L. Milor

引用次数: 25

Design techniques of eNVM-enabled neuromorphic computing systems 基于envm的神经形态计算系统设计技术

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753356

Chang Song, Beiye Liu, Chenchen Liu, Hai Helen Li, Yiran Chen

引用次数: 4

Ultra-low energy security circuits for IoT applications 物联网应用的超低能耗安全电路

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753358

Sudhir K. Satpathy, S. Mathew, Vikram B. Suresh, R. Krishnamurthy

{"title":"Ultra-low energy security circuits for IoT applications","authors":"Sudhir K. Satpathy, S. Mathew, Vikram B. Suresh, R. Krishnamurthy","doi":"10.1109/ICCD.2016.7753358","DOIUrl":"https://doi.org/10.1109/ICCD.2016.7753358","url":null,"abstract":"Low-area energy-efficient security primitives are key building blocks for enabling end-to-end content protection, user authentication, and consumer confidentiality in the IoT world that is estimated to surpass 50billion smart and connected devices by 2020. This paper describes design approaches that blend energy-efficient circuit techniques with optimal accelerator microarchitecture datapath, and hardware friendly arithmetic to achieve ultra-low energy consumption in security platforms for seamless adoption in area/battery constrained and self-powered systems. Industry leading energy-efficiency is demonstrated with three designs, fabricated and measured in advanced process technologies: 1) A 2040-gate arithmetically optimized composite-field Sbox based AES accelerator achieves 289Gbps/W peak energy-efficiency while offering 432Mbps throughput in 22nm tri-gate CMOS, 2) Hybrid Physically Unclonable Function (PUF) circuit leverages burn-in induced aging to reduce bit-error, followed by temporal-majority-voting, dark-bit masking, and error-correction conditioning techniques to generate a 100% stable full-entropy key with 190fJ/bit energy consumption in 22nm tri-gate CMOS. 3) A light-weight all digital TRNG uses in-line correlation suppressor and entropy-extractor circuits to achieve >0.99 min-entropy with 3pJ/bit measured energy-efficiency while operating down to 300mV in 14nm tri-gate CMOS.","PeriodicalId":297899,"journal":{"name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133302646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

DLL: A dynamic latency-aware load-balancing strategy in 2.5D NoC architecture 2.5D NoC架构中的动态延迟感知负载平衡策略

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753352

Chen Li, Sheng Ma, Lu Wang, Zicong Wang, Xia Zhao, Yang Guo

{"title":"DLL: A dynamic latency-aware load-balancing strategy in 2.5D NoC architecture","authors":"Chen Li, Sheng Ma, Lu Wang, Zicong Wang, Xia Zhao, Yang Guo","doi":"10.1109/ICCD.2016.7753352","DOIUrl":"https://doi.org/10.1109/ICCD.2016.7753352","url":null,"abstract":"As the 3D stacking technology still faces several challenges, the 2.5D stacking technology gains better application prospects nowadays. With the silicon interposer, the 2.5D stacking can improve the bandwidth and capacity of the memory system. To satisfy the communication requirements of the integrated memory system, the free routing resources in the interposer should be explored to implement an additional network. Yet, the performance is strongly limited by the unbalanced loads between the CPU-layer network and the interposer-layer network. In this paper, to address this issue, we propose a dynamic latency-aware load-balancing (DLL) strategy. Our key innovations are detecting congestion of the network layer via the average latency of recent packets and making the network layer selection at each source node. We leverage the free routing resources in the interposer to implement a latency propagation ring. With the ring, the latency information tracked at destination nodes is propagated back to source nodes. We achieve load-balance by using these information. Experimental results show that compared with the baseline design, a destination-detection strategy and a buffer-aware strategy, our DLL strategy achieves 45%, 14.9% and 6.5% of average throughput improvements with minor overheads.","PeriodicalId":297899,"journal":{"name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","volume":"29 42","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132275549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

FPGA Trust Zone: Incorporating trust and reliability into FPGA designs FPGA信任区:将信任和可靠性纳入FPGA设计

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753346

V. Jyothi, Manasa Thoonoli, Richard Stern, R. Karri

引用次数: 19

Memos: A full hierarchy hybrid memory management framework 备忘录:一个完整的层次混合内存管理框架

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753305

Lei Liu, Hao Yang, Yong Li, Mengyao Xie, Lian Li, Chenggang Wu

引用次数: 19

Strategies for optimal operating point selection in timing speculative processors 时序推测处理器中最佳工作点选择策略

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753344

Omid Assare, Rajesh K. Gupta

引用次数: 1

Scalable memory architecture for soft-core processors 用于软核处理器的可扩展内存架构

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753312

T. Jost, G. Nazar, L. Carro

引用次数: 2

BADGR: A practical GHR implementation for TAGE branch predictors BADGR:用于TAGE分支预测器的实用GHR实现

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753338

David J. Schlais, Mikko H. Lipasti

引用次数: 5

Adaptive and flexible key-value stores through soft data partitioning 通过软数据分区自适应灵活的键值存储

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753293

B. Hong, Yongkee Kwon, Jung Ho Ahn, John Kim

{"title":"Adaptive and flexible key-value stores through soft data partitioning","authors":"B. Hong, Yongkee Kwon, Jung Ho Ahn, John Kim","doi":"10.1109/ICCD.2016.7753293","DOIUrl":"https://doi.org/10.1109/ICCD.2016.7753293","url":null,"abstract":"Key-value stores such as Memcached have become widely used by cloud and web-service providers. While there has been a significant amount of research done on improving the absolute performance of key-value stores, this work proposes an adaptive and a flexible approach to key-value stores. We first propose soft data partitioning that divides memory into multiple groups within a single node, or a single server process, to enable scale-up of key-value stores, while providing NUMA locality and an adaptive approach that can reduce overall request miss rate. The soft-partitioning enables a flexible Memcached server implementation in a NUMA system through NUMA-aware allocation as well as power-efficient NUMA server operation by migrating frequently accessed key-value pairs among the groups. We also propose an adaptive replacement policy within Memcached server that compares miss rates across the different memory groups to determine a more optimal replacement policy. To overcome the limitation of partitioning, we propose Group Auto-Balancing (GAB) where memory allocation from the different groups can be borrowed to minimize miss rate. Our results improve Memcached throughput by 12.9%, on average, over previously proposed MemC3 algorithm (up to 3.1× for write intensive workloads) while the adaptive replacement policy shows the lowest miss rate on adversarial access patterns.","PeriodicalId":297899,"journal":{"name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132536547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2