2014 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)最新文献

Methodology for electromigration signoff in the presence of adaptive voltage scaling 自适应电压标度下的电迁移信号方法

2014 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2014-06-01 DOI: 10.1145/2633948.2633954

W. Chan, A. Kahng, S. Nath

{"title":"Methodology for electromigration signoff in the presence of adaptive voltage scaling","authors":"W. Chan, A. Kahng, S. Nath","doi":"10.1145/2633948.2633954","DOIUrl":"https://doi.org/10.1145/2633948.2633954","url":null,"abstract":"Electromigration (EM) is a growing reliability concern in sub-22nm technology. Design teams must apply guardbands to meet EM lifetime requirements, at the cost of performance and power. However, EM lifetime analysis cannot ignore front-end reliability mechanisms such as bias temperature instability (BTl). Although the gate delay degradation due to BTI can be compensated by adaptive voltage scaling (AVS), nay elevated supply voltage will accelerate EM degradation and reduce lifetime. Since the degradation of BTI is front-loaded, AVS can increase electrical stress on metal wires relatively early during IC lifetime, which can significantly decrease electromigration reliability. In this paper, we study the \"chicken-egg\" interlock among BTI, AVS and EM and quantify timing and power costs of meeting EM lifetime requirements with full consideration of BTI and AVS mechanisms. By applying existing statistical and physical EM models, we demonstrate that without such considerations, the inaccuracy (reduction) of EM lifetime due to improper guardband against BTI at signoff can be as high as 30% in a 2Snm FDSOI foundry technology. Furthermore, we provide signoff guidelines which suggest that the lifetime penalty can be compensated by paying a penalty of up to 1.6% in area and 6% in power. We also demonstrate that suboptimal choice of voltage step size and scheduling strategy can result in up to 1.5 years of decreased EM lifetime.","PeriodicalId":225756,"journal":{"name":"2014 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134121484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Power network-on-chip for scalable power delivery 用于可扩展电力输送的片上电网

2014 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2014-06-01 DOI: 10.1145/2633948.2633949

Inna Vaisband, E. Friedman

{"title":"Power network-on-chip for scalable power delivery","authors":"Inna Vaisband, E. Friedman","doi":"10.1145/2633948.2633949","DOIUrl":"https://doi.org/10.1145/2633948.2633949","url":null,"abstract":"Delivering high quality power to the on-chip circuitry with minimum energy loss is an essential component of integrated circuits. The quality of the power supply can be efficiently addressed with multiple power supplies and decoupling capacitors integrated on-chip close to the points-of-load. Distributed power delivery requires the co-design of hundreds of power converters with thousands of decoupling capacitors and billions of current loads within multiple power domains, significantly increasing the design complexity of existing power delivery systems. Efficient real-time management of the power budget in these complicated distributed power delivery systems is impractical with existing ad hoc approaches. The concept of a power network on-chip (PNoC) is introduced here as a systematic methodological solution for on-chip power delivery and management that provides enhanced power control and real-time management of resource sharing. A PNoC with four power domains is investigated based on the proposed architecture, and circuits for sensing, routing, and dynamic control of the on-chip power are described. The built-in modularity of the PNoC is exploited to apply dynamic voltage scaling, illustrating the scalability of the PNoC platform, while exhibiting power savings of up to 32%.","PeriodicalId":225756,"journal":{"name":"2014 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134227482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Pacman: driving nonuniform clock grid loads for low-skew robust clock network 吃豆人:驱动低倾斜鲁棒时钟网络的非均匀时钟网格负载

2014 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2014-06-01 DOI: 10.1145/2633948.2633953

Nancy Y. Zhou, P. Restle, Joseph N. Palumbo, J. Kozhaya, Haifeng Qian, Zhou Li, C. Alpert, C. Sze

{"title":"Pacman: driving nonuniform clock grid loads for low-skew robust clock network","authors":"Nancy Y. Zhou, P. Restle, Joseph N. Palumbo, J. Kozhaya, Haifeng Qian, Zhou Li, C. Alpert, C. Sze","doi":"10.1145/2633948.2633953","DOIUrl":"https://doi.org/10.1145/2633948.2633953","url":null,"abstract":"Clock grid is a mainstream clock network methodology for high performance microprocessor and SOC designs. Clock skew, power usage and robustness to PVT (power, voltage, temperature) are all important metrics for a high quality clock grid design. Tree-driven-grid clock network is a typical clock grid clock network. It includes a clock source, a buffered tree, leaf buffers, a mesh clock grid, local clock buffers, and latches as shown in Fig. 1. For such network, one big challenge is how to connect the leaf level buffers of the global tree to the grid with nonuniform loads under tigh slew and skew constrainsts. The choice of tapping points that connect the leaf buffers to the clock grid are critical to the quality of te clock designs. Good tapping points can minimize the clock skew and reduce power. In this paper, we proposed a new algorithm to select the tapping points to build the global tree as regular and symmetric as possible. From our experimental results, the proposed algorithm can efficiently reduce global clock skew, rising slew, maximum overshoot, reduce power, and avoid local skew violation.","PeriodicalId":225756,"journal":{"name":"2014 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115176563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

UI-route: An ultra-fast incremental maze routing algorithm UI-route:一种超快速增量迷宫路由算法

2014 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2014-06-01 DOI: 10.1145/2633948.2633952

Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong

{"title":"UI-route: An ultra-fast incremental maze routing algorithm","authors":"Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong","doi":"10.1145/2633948.2633952","DOIUrl":"https://doi.org/10.1145/2633948.2633952","url":null,"abstract":"Grid-based maze routing is a fundamental problem in electronic-design-automation (EDA) domain. A core primitive deals with a large query set about route connectivity subject to incremental changes on grid graph. Existing approaches pertain to batch processing, where each route query is independently and repeatedly solved by a routing procedure. Few researches so far discuss an efficient utilization of search knowledge in incremental fashion, which could dramatically speed up the search. Unfortunately, existing algorithms nearly rely on irregular and highly divergent search space, imposing acceleration challenges on refitting them to incremental version. Consequently, in this paper we present UI-Route, an ultra-fast incremental maze routing algorithm in grid environment. UI-Route is unique in breaking route equivalence, proving that a huge amount of equivalent search efforts can be optimally and incrementally eliminated. Equivalence breaking enables regularized search space, delivering well-tabulated search knowledge through the incremental processing. Moreover UI-Route is largely orthogonal to many applications built upon maze routing and therefore can seamlessly substitute for speedup. Experimental results on a set of modern circuit benchmarks demonstrate that UI-Route achieves prominent speedup over existing algorithms.","PeriodicalId":225756,"journal":{"name":"2014 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125332140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Compact models and model standard for 2.5D and 3D integration 紧凑的模型和模型标准的2.5D和3D集成

2014 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2014-06-01 DOI: 10.1145/2633948.2633955

Qiaosha Zou, Yuan Xie

引用次数: 0