COSMIC '13最新文献

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Automatic speculative parallelization of loops using polyhedral dependence analysis 利用多面体相关性分析的自动推测并行化循环

COSMIC '13 Pub Date : 2013-02-24 DOI: 10.1145/2446920.2446921

Arnamoy Bhattacharyya, J. N. Amaral

引用次数: 9

Fast dynamic binary rewriting to support thread migration in shared-ISA asymmetric multicores 快速动态二进制重写，支持共享isa非对称多核中的线程迁移

COSMIC '13 Pub Date : 2013-02-24 DOI: 10.1145/2446920.2446924

G. Georgakoudis, Dimitrios S. Nikolopoulos, S. Lalis

{"title":"Fast dynamic binary rewriting to support thread migration in shared-ISA asymmetric multicores","authors":"G. Georgakoudis, Dimitrios S. Nikolopoulos, S. Lalis","doi":"10.1145/2446920.2446924","DOIUrl":"https://doi.org/10.1145/2446920.2446924","url":null,"abstract":"Asymmetric multicore processors have demonstrated a strong potential for improving performance and energy-efficiency. Shared-ISA asymmetric multicore processors overcome programmability problems in disjoint-ISA systems and enhance single-ISA architectures with instruction based asymmetry. In such a design, processors share a common, baseline ISA and performance enhanced (PE) cores extend the baseline ISA with instructions that accelerate performance-critical operations. To exploit asymmetry, the scheduler should be able to migrate threads based on their acceleration potential.\u0000 The contribution of this paper is a low overhead binary code rewriting method for shared-ISA multicore processors that transforms a binary executable at runtime, according to the scheduled processor's PE capabilities. The mutable binary code can be re-targeted among heterogeneous cores at any point in execution while preserving functional equivalence and using PE instructions, transparently, when available, thus enabling migrations among heterogeneous cores. We emulate a realistic shared-ISA asymmetric multicore system using actual hardware -- an FPGA experimental prototype. Experimental analysis shows that dynamic binary rewriting is feasible with little overhead. Rewritten code speeds up successfully baseline code while performing close, with 70% average efficiency, to non-portable, compiler generated code, statically optimized to use PE instructions.","PeriodicalId":224968,"journal":{"name":"COSMIC '13","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133276662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

MIC acceleration of short-range molecular dynamics simulations 短程分子动力学模拟的MIC加速

COSMIC '13 Pub Date : 2013-02-24 DOI: 10.1145/2446920.2446922

Qiang Wu, Canqun Yang, T. Tang, Liquan Xiao

{"title":"MIC acceleration of short-range molecular dynamics simulations","authors":"Qiang Wu, Canqun Yang, T. Tang, Liquan Xiao","doi":"10.1145/2446920.2446922","DOIUrl":"https://doi.org/10.1145/2446920.2446922","url":null,"abstract":"Heterogeneous systems containing accelerators such as GPUs or co-processors such as Intel MIC are becoming more prevalent due to their ability of exploiting large-scale parallelism in applications. In this paper, we have developed a hierarchical parallelization scheme for molecular dynamics simulations on CPU-MIC heterogeneous systems. The scheme exploits multi-level parallelism combining (1) task-level parallelism using a tightly-coupled division method, (2) thread-level parallelism employing spatial-decomposition through dynamically scheduled multi-threading, and (3) data-level parallelism via SIMD technology.\u0000 By employing a hierarchy of parallelism with several optimization methods such as memory latency hiding and data pre-fetching, our MD code running on a CPU-MIC heterogeneous system (one 2.60GHZ eight-core Intel Xeon E5-2670 CPU and one 57-core Intel Knight Corner co-processor) achieves (1) multi-thread parallel efficiency of 72.4% for 57 threads on the co-processor with up to 7.62 times SIMD speedup on each core for the force computation task, and (2) up to 2.25 times speedup on the CPU-MIC system over the pure CPU system, which outperforms our previous work on a CPU-GPU (one NVIDIA Tesla M2050) platform. Our work shows that MD simulations can benefit enormously from the CPU-MIC heterogeneous platforms.","PeriodicalId":224968,"journal":{"name":"COSMIC '13","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123604214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14