{"title":"Timed Verification of Asynchronous Circuits","authors":"Jesper B. Møller, H. Hulgaard, H. Andersen","doi":"10.1007/3-540-36190-1_8","DOIUrl":"https://doi.org/10.1007/3-540-36190-1_8","url":null,"abstract":"","PeriodicalId":165704,"journal":{"name":"Concurrency and Hardware Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121575849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi, Yosinori Watanabe
{"title":"Modeling and Designing Heterogeneous Systems","authors":"F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi, Yosinori Watanabe","doi":"10.1007/3-540-36190-1_7","DOIUrl":"https://doi.org/10.1007/3-540-36190-1_7","url":null,"abstract":"","PeriodicalId":165704,"journal":{"name":"Concurrency and Hardware Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131872433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Functional and Performance Modeling of Concurrency in VCC","authors":"W. LaRue, Sherry Solden, Bishnupriya Bhattacharya","doi":"10.1007/3-540-36190-1_6","DOIUrl":"https://doi.org/10.1007/3-540-36190-1_6","url":null,"abstract":"","PeriodicalId":165704,"journal":{"name":"Concurrency and Hardware Design","volume":"4 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131639464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance Analysis of Asynchronous Circuits Using Markov Chains","authors":"P. Beerel, A. Xie","doi":"10.1007/3-540-36190-1_9","DOIUrl":"https://doi.org/10.1007/3-540-36190-1_9","url":null,"abstract":"","PeriodicalId":165704,"journal":{"name":"Concurrency and Hardware Design","volume":"723 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133766217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Synthesis of Reactive Systems: Application to Asynchronous Circuit Design","authors":"J. Carmona, J. Cortadella, E. Pastor","doi":"10.1007/3-540-36190-1_4","DOIUrl":"https://doi.org/10.1007/3-540-36190-1_4","url":null,"abstract":"","PeriodicalId":165704,"journal":{"name":"Concurrency and Hardware Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132660762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Programming Approach to the Design of Asynchronous Logic Blocks","authors":"M. B. Josephs, D. Furey","doi":"10.1007/3-540-36190-1_2","DOIUrl":"https://doi.org/10.1007/3-540-36190-1_2","url":null,"abstract":"","PeriodicalId":165704,"journal":{"name":"Concurrency and Hardware Design","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122829723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}