Introduction to Logic Circuits & Logic Design with Verilog最新文献

筛选
英文 中文
Programmable Logic 可编程逻辑
Introduction to Logic Circuits & Logic Design with Verilog Pub Date : 1900-01-01 DOI: 10.1007/978-3-030-12489-2_11
B. Lameres
{"title":"Programmable Logic","authors":"B. Lameres","doi":"10.1007/978-3-030-12489-2_11","DOIUrl":"https://doi.org/10.1007/978-3-030-12489-2_11","url":null,"abstract":"","PeriodicalId":158563,"journal":{"name":"Introduction to Logic Circuits & Logic Design with Verilog","volume":"51 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122406834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Verilog (Part 1) Verilog(第一部分)
Introduction to Logic Circuits & Logic Design with Verilog Pub Date : 1900-01-01 DOI: 10.1007/978-3-319-53883-9_5
B. Lameres
{"title":"Verilog (Part 1)","authors":"B. Lameres","doi":"10.1007/978-3-319-53883-9_5","DOIUrl":"https://doi.org/10.1007/978-3-319-53883-9_5","url":null,"abstract":"","PeriodicalId":158563,"journal":{"name":"Introduction to Logic Circuits & Logic Design with Verilog","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130839537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Introduction: Analog Versus Digital 介绍:模拟与数字
Introduction to Logic Circuits & Logic Design with Verilog Pub Date : 1900-01-01 DOI: 10.1007/978-3-030-13605-5_1
B. Lameres
{"title":"Introduction: Analog Versus Digital","authors":"B. Lameres","doi":"10.1007/978-3-030-13605-5_1","DOIUrl":"https://doi.org/10.1007/978-3-030-13605-5_1","url":null,"abstract":"","PeriodicalId":158563,"journal":{"name":"Introduction to Logic Circuits & Logic Design with Verilog","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132552834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Memory 内存
Introduction to Logic Circuits & Logic Design with Verilog Pub Date : 1900-01-01 DOI: 10.1007/978-3-030-12489-2_10
B. Lameres
{"title":"Memory","authors":"B. Lameres","doi":"10.1007/978-3-030-12489-2_10","DOIUrl":"https://doi.org/10.1007/978-3-030-12489-2_10","url":null,"abstract":"","PeriodicalId":158563,"journal":{"name":"Introduction to Logic Circuits & Logic Design with Verilog","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116651417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Computer System Design 计算机系统设计
Introduction to Logic Circuits & Logic Design with Verilog Pub Date : 1900-01-01 DOI: 10.1007/978-3-319-34195-8_13
B. Lameres
{"title":"Computer System Design","authors":"B. Lameres","doi":"10.1007/978-3-319-34195-8_13","DOIUrl":"https://doi.org/10.1007/978-3-319-34195-8_13","url":null,"abstract":"","PeriodicalId":158563,"journal":{"name":"Introduction to Logic Circuits & Logic Design with Verilog","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124537485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Verilog (Part 2) Verilog(第2部分)
Introduction to Logic Circuits & Logic Design with Verilog Pub Date : 1900-01-01 DOI: 10.1007/978-3-319-53883-9_8
B. Lameres
{"title":"Verilog (Part 2)","authors":"B. Lameres","doi":"10.1007/978-3-319-53883-9_8","DOIUrl":"https://doi.org/10.1007/978-3-319-53883-9_8","url":null,"abstract":"","PeriodicalId":158563,"journal":{"name":"Introduction to Logic Circuits & Logic Design with Verilog","volume":"2012 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114027452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MSI Logic MSI逻辑
Introduction to Logic Circuits & Logic Design with Verilog Pub Date : 1900-01-01 DOI: 10.1007/978-3-030-13605-5_6
B. Lameres
{"title":"MSI Logic","authors":"B. Lameres","doi":"10.1007/978-3-030-13605-5_6","DOIUrl":"https://doi.org/10.1007/978-3-030-13605-5_6","url":null,"abstract":"","PeriodicalId":158563,"journal":{"name":"Introduction to Logic Circuits & Logic Design with Verilog","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115043764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信