{"title":"Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design","authors":"F. Mo, R. Brayton","doi":"10.1007/b117043","DOIUrl":"https://doi.org/10.1007/b117043","url":null,"abstract":"","PeriodicalId":142229,"journal":{"name":"International Workshop on Logic & Synthesis","volume":"36 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123531506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Binary time-frame expansion","authors":"F. Fallah","doi":"10.1145/774572.774639","DOIUrl":"https://doi.org/10.1145/774572.774639","url":null,"abstract":"This paper introduces a new method for performing time-frame expansion based on writing the number of time frames in terms of powers of two. In the proposed method, the behavior of a circuit for t time frames, where n 0 ⪣t < n is modeled by unrolling the circuit 20, 21, 22, ..., 2(log n −1) times and combining them. This formulation of the problem makes it possible to prune the search space quickly when the problem is infeasible. To show the advantage of this method, we have used it to model the state justification problem and solve the problem using a SAT-solver. Experimental results show several orders of magnitude speedup for some non-trivial infeasible problems. Furthermore, in most cases the CPU time requirement grows linearly in terms of the number of time frames.","PeriodicalId":142229,"journal":{"name":"International Workshop on Logic & Synthesis","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124192674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Predictability: definition, ananlysis and optimization","authors":"Ankur Srivastava, M. Sarrafzadeh","doi":"10.1145/774572.774589","DOIUrl":"https://doi.org/10.1145/774572.774589","url":null,"abstract":"Predictability is the quantified from of accuracy. We propose a predictability driven design methodology. The novelty lies in defining and using the idea of predictability. In order to illustrate the basic concepts we focus on the low power binding problem. The binding problem for low power was solved in [3], [5], but in the presence of in-accuracies, their claims of optimality are imprecise. Our experiments show that these inaccuracies could be as high as 33%. Our methodology could improve this unpredictability to as low as 11% with minimal power penalty (7% on average).","PeriodicalId":142229,"journal":{"name":"International Workshop on Logic & Synthesis","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125120386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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