2021 IEEE/ACM 7th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC)最新文献

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2021 IEEE/ACM 7th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC) Pub Date : 2021-11-01 DOI: 10.1109/llvmhpc54804.2021.00002

引用次数: 0

Facilitating CoDesign with Automatic Code Similarity Learning 用自动代码相似度学习促进协同设计

2021 IEEE/ACM 7th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC) Pub Date : 2021-11-01 DOI: 10.1109/llvmhpc54804.2021.00011

T. Nguyen, E. Strohmaier, J. Shalf

引用次数: 0

Flacc: Towards OpenACC support for Fortran in the LLVM Ecosystem Flacc:在LLVM生态系统中实现对Fortran的OpenACC支持

2021 IEEE/ACM 7th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC) Pub Date : 2021-11-01 DOI: 10.1109/llvmhpc54804.2021.00007

Valentin Clement, J. Vetter

{"title":"Flacc: Towards OpenACC support for Fortran in the LLVM Ecosystem","authors":"Valentin Clement, J. Vetter","doi":"10.1109/llvmhpc54804.2021.00007","DOIUrl":"https://doi.org/10.1109/llvmhpc54804.2021.00007","url":null,"abstract":"OpenACC is a directive-based programming model for heterogeneous accelerators initially launched in 2010 to provide a portable solution at a level of abstraction above OpenCL, CUDA, and other lower-level programming models. Various implementations of OpenACC for C, C++, and Fortran exist; however, only one open-source, production implementation of OpenACC for Fortran does exist. Moreover, most contemporary compiler tool chains for heterogeneous computing are based on LLVM. This lack of support poses a serious risk for high-performance computing application developers targeting GPUs and other accelerators, and it limits the ability of the community to experiment with, extend, and contribute to the OpenACC specification and open-source implementation itself. To address this gap, we have designed and begun implementing Flacc: an effort funded by the US Exascale Computing Project to develop production OpenACC compiler support for Fortran based on Flang within the LLVM ecosystem. In this paper, we describe the Flacc goals, initial design and prototype, and challenges that we have encountered so far in our prototyping efforts. Flacc is implemented as a MLIR dialect in the Flang Fortran front end in LLVM. The Flacc front end currently supports OpenACC version 3.1, and the Flacc run time is currently under development and relies on contributions from the Clacc project. Current contributions to Flacc are available in the main ${color{Green}{mathbf{LLVM}};{mathbf{repository}}}$.1","PeriodicalId":140581,"journal":{"name":"2021 IEEE/ACM 7th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC)","volume":"13 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133774355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A High Performance Sparse Tensor Algebra Compiler in MLIR MLIR中高性能稀疏张量代数编译器

2021 IEEE/ACM 7th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC) Pub Date : 2021-11-01 DOI: 10.1109/llvmhpc54804.2021.00009

Ruiqin Tian, Luanzheng Guo, Jiajia Li, Bin Ren, Gokcen Kestor

{"title":"A High Performance Sparse Tensor Algebra Compiler in MLIR","authors":"Ruiqin Tian, Luanzheng Guo, Jiajia Li, Bin Ren, Gokcen Kestor","doi":"10.1109/llvmhpc54804.2021.00009","DOIUrl":"https://doi.org/10.1109/llvmhpc54804.2021.00009","url":null,"abstract":"Sparse tensor algebra is widely used in many applications, including scientific computing, machine learning, and data analytics. The performance of sparse tensor algebra kernels strongly depends on the intrinsic characteristics of the input tensors, hence many storage formats are designed for tensors to achieve optimal performance for particular applications/architectures, which makes it challenging to implement and optimize every tensor operation of interest on a given architecture. We propose a tensor algebra domain-specific language (DSL) and compiler framework to automatically generate kernels for mixed sparse-dense tensor algebra operations. The proposed DSL provides high-level programming abstractions that resemble the familiar Einstein notation to represent tensor algebra operations. The compiler introduces a new Sparse Tensor Algebra dialect built on top of LLVM’s extensible MLIR compiler infrastructure for efficient code generation while covering a wide range of tensor storage formats. Our compiler also leverages input-dependent code optimization to enhance data locality for better performance. Our results show that the performance of automatically generated kernels outperforms the state-of-the-art sparse tensor algebra compiler, with up to 20.92x, 6.39x, and 13.9x performance improvement over state-of-the-art tensor algebra compilers, for parallel SpMV, SpMM, and TTM, respectively.","PeriodicalId":140581,"journal":{"name":"2021 IEEE/ACM 7th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC)","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133748294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

OpenMP aware MHP Analysis for Improved Static Data-Race Detection 基于OpenMP的MHP分析改进静态数据竞争检测

2021 IEEE/ACM 7th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC) Pub Date : 2021-11-01 DOI: 10.1109/LLVMHPC54804.2021.00006

Utpal Bora, Shraiysh Vaishay, Saurabh Joshi, Ramakrishna Upadrasta

{"title":"OpenMP aware MHP Analysis for Improved Static Data-Race Detection","authors":"Utpal Bora, Shraiysh Vaishay, Saurabh Joshi, Ramakrishna Upadrasta","doi":"10.1109/LLVMHPC54804.2021.00006","DOIUrl":"https://doi.org/10.1109/LLVMHPC54804.2021.00006","url":null,"abstract":"Data races, a major source of bugs in concurrent programs, can result in loss of manpower and time as well as data loss due to system failures. OpenMP, the de facto shared memory parallelism framework used in the HPC community, also suffers from data races. To detect race conditions in OpenMP programs and improve turnaround time and/or developer productivity, we present a data flow analysis based, fast, static data race checker in the LLVM compiler framework. Our tool can detect races in the presence or absence of explicit barriers, with implicit or explicit synchronization. In addition, our tool effectively works for the OpenMP target offloading constructs and also supports the frequently used OpenMP constructs.We formalize and provide a data flow analysis framework to perform Phase Interval Analysis (PIA) of OpenMP programs. Phase intervals are then used to compute the MHP (and its complement NHP) sets for the programs, which, in turn, are used to detect data races statically.We evaluate our work using multiple OpenMP race detection benchmarks and real world applications. Our experiments show that the checker is comparable to the state-of-the-art in various performance metrics with around 90% accuracy, almost perfect recall, and significantly lower runtime and memory footprint.","PeriodicalId":140581,"journal":{"name":"2021 IEEE/ACM 7th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC)","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123264396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Extending LLVM IR for DPC++ Matrix Support: A Case Study with Intel® Advanced Matrix Extensions (Intel® AMX) 为dpc++矩阵支持扩展LLVM IR:使用Intel®高级矩阵扩展(Intel®AMX)的案例研究

2021 IEEE/ACM 7th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC) Pub Date : 2021-11-01 DOI: 10.1109/llvmhpc54804.2021.00008

Dounia Khaldi, Yuanke Luo, Bing Yu, A. Sotkin, B. Morais, M. Girkar

引用次数: 1

Toward an Automated Hardware Pipelining LLVM Pass Infrastructure 面向自动化硬件流水线的LLVM通道基础架构

2021 IEEE/ACM 7th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC) Pub Date : 2021-11-01 DOI: 10.1109/llvmhpc54804.2021.00010

John D. Leidel, Ryan Kabrick, D. Donofrio

引用次数: 0

[Title page] (标题页)

2021 IEEE/ACM 7th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC) Pub Date : 2021-11-01 DOI: 10.1109/llvmhpc54804.2021.00001

引用次数: 0