Proceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores最新文献

Bounded incoherence: a programming model for non-cache-coherent shared memory architectures 有限不相干:非缓存一致共享内存架构的编程模型

Proceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores Pub Date : 2020-02-22 DOI: 10.1145/3380536.3380541

Yuxin Ren, Gabriel Parmer, D. Milojicic

{"title":"Bounded incoherence: a programming model for non-cache-coherent shared memory architectures","authors":"Yuxin Ren, Gabriel Parmer, D. Milojicic","doi":"10.1145/3380536.3380541","DOIUrl":"https://doi.org/10.1145/3380536.3380541","url":null,"abstract":"Cache coherence in modern computer architectures enables easier programming by sharing data across multiple processors. Unfortunately, it can also limit scalability due to cache coherency traffic initiated by competing memory accesses. Rack-scale systems introduce shared memory across a whole rack, but without inter-node cache coherence. This poses memory management and concurrency control challenges for applications that must explicitly manage cache-lines. To fully utilize rack-scale systems for low-latency and scalable computation, applications need to maintain cached memory accesses in spite of non-coherency. This paper introduces Bounded Incoherence, a programming and memory consistency model that enables cached access to shared data-structures in non-cache-coherency memory. It ensures that updates to memory on one node are visible within at most a bounded amount of time on all other nodes. We evaluate this memory model on modified PowerGraph graph processing framework, and boost its performance by 30% with eight sockets by enabling cached-access to data-structures.","PeriodicalId":127938,"journal":{"name":"Proceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130364050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Towards a portable hierarchical view of distributed shared memory systems: challenges and solutions 面向分布式共享内存系统的可移植分层视图:挑战和解决方案

Proceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores Pub Date : 2020-02-22 DOI: 10.1145/3380536.3380542

Millad Ghane, S. Chandrasekaran, M. Cheung

{"title":"Towards a portable hierarchical view of distributed shared memory systems: challenges and solutions","authors":"Millad Ghane, S. Chandrasekaran, M. Cheung","doi":"10.1145/3380536.3380542","DOIUrl":"https://doi.org/10.1145/3380536.3380542","url":null,"abstract":"An ever-growing diversity in the architecture of modern super-computers has led to challenges in developing scientific software. Utilizing heterogeneous and disruptive architectures (e.g., off-chip and, in the near future, on-chip accelerators) has increased the software complexity and worsened its maintainability. To that end, we need a productive software ecosystem that improves the usability and portability of applications for such systems while allowing every parallelism opportunity to be exploited. In this paper, we outline several challenges that we encountered in the implementation of Gecko, a hierarchical model for distributed shared memory architectures, using a directive-based programming model, and discuss our solutions. Such challenges include: 1) inferred kernel execution with respect to the data placement, 2) workload distribution, 3) hierarchy maintenance, and 4) memory management. We performed the experimental evaluation of our implementation by using the Stream and Rodinia benchmarks. These benchmarks represent several major scientific software applications commonly used by the domain scientists. Our results reveal how the Stream benchmark reaches a sustainable bandwidth of 80 GB/s and 1.8 TB/s for single Intel Xeon Processor and four NVIDIA V100 GPUs, respectively. Additionally, the srad_v2 in the Rodinia benchmark reaches the 88% speedup efficiency while using four GPUs.","PeriodicalId":127938,"journal":{"name":"Proceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128876426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

TardisTM

Proceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores Pub Date : 2020-02-19 DOI: 10.1145/3380536.3380538

Daming D. Chen, Phillip B. Gibbons, T. Mowry

引用次数: 1

Lock-free transactional vector 无锁事务矢量

Proceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores Pub Date : 2020-02-19 DOI: 10.1145/3380536.3380543

Kenneth Lamar, Christina L. Peterson, D. Dechev

{"title":"Lock-free transactional vector","authors":"Kenneth Lamar, Christina L. Peterson, D. Dechev","doi":"10.1145/3380536.3380543","DOIUrl":"https://doi.org/10.1145/3380536.3380543","url":null,"abstract":"The vector is a fundamental data structure, offering constant-time traversal to elements and a dynamically resizable range of indices. While several concurrent vectors exist, a composition of concurrent vector operations dependent on each other can lead to undefined behavior. Techniques for providing transactional capabilities for data structure operations include Software Transactional Memory (STM) and transactional transformation methodologies. Transactional transformations convert concurrent data structures into their transactional equivalents at an operation level, rather than STM's object or memory level. To the best of our knowledge, existing STMs do not support dynamic read/write sets in a lock-free manner, and transactional transformation methodologies are unsuitable for the vector's contiguous memory layout. In this work, we present the first lock-free transactional vector. It integrates the fast lock-free resizing and instant logical status changes from related works. Our approach pre-processes transactions to reduce shared memory access and simplify access logic. This can be done without locking elements or verifying conflicts between transactions. We compare our design against state-of-the-art transactional designs, GCC STM, Transactional Boosting, and STO. All data structures are tested on four different platforms, including x86_64 and ARM architectures. We find that our lock-free transactional vector generally offers better scalability than STM and STO, and competitive performance with Transactional Boosting, but with additional lock-free guarantees. In scenarios with only reads and writes, our vector is as much as 47% faster than Transactional Boosting.","PeriodicalId":127938,"journal":{"name":"Proceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores","volume":"832 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132027087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

ELSE 其他的

Proceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores Pub Date : 2020-02-19 DOI: 10.1145/3380536.3380545

Xiaoxin Tang

{"title":"ELSE","authors":"Xiaoxin Tang","doi":"10.1145/3380536.3380545","DOIUrl":"https://doi.org/10.1145/3380536.3380545","url":null,"abstract":"Unlike general systems, hardware and software of embedded systems are usually customized for specific purposes and many of them are real-time systems. With time changing, their workloads are also changing rapidly and maintaining their software becomes a complicated job. The key is to understand their behaviours so that developers can make changes to them according to the new situations. To trace their runtime behaviours, instrumentation techniques are widely used in general systems. However, applying them on embedded system faces several problems including big size growth rate, long instrumentation time, high runtime overhead, etc. As the hardware performance of embedded system are usually limited, these problems are crucial and cannot be ignored. As far as we know, existing tools can only partly solve all these problems. In this paper, we propose ELSE, an Efficient and Link-time, Static instrumentation tool for Embedded system. It supports efficient low-level and high-level instrumentation to collect most runtime information developers want. It does not waste any space during instrumentation thus its size growth rate is very small, which is only about 30% of other existing tools. Its processing time is also orders of magnitude less than other existing tools. We optimize the influence of registers and cache which can further reduce its runtime overhead. Overall, ELSE performs the best compared with other state-of-the-art tools on SPEC 2006 benchmarks.","PeriodicalId":127938,"journal":{"name":"Proceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121231873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Self-adjusting task granularity for Global load balancer library on clusters of many-core processors 多核处理器集群上的全局负载平衡器库的自调整任务粒度

Proceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores Pub Date : 2020-02-19 DOI: 10.1145/3380536.3380539

Patrick Finnerty, Tomio Kamada, C. Ohta

{"title":"Self-adjusting task granularity for Global load balancer library on clusters of many-core processors","authors":"Patrick Finnerty, Tomio Kamada, C. Ohta","doi":"10.1145/3380536.3380539","DOIUrl":"https://doi.org/10.1145/3380536.3380539","url":null,"abstract":"Achieving load balance is a challenge for irregular applications. Balancing runtimes and libraries aim at relieving the programmer from this difficult task by proposing a layer of abstraction between the computation at hand and the hardware used to actually perform it. With the rise of many-core architectures, load balancers for distributed computation are now expected to handle unbalance both between and within compute nodes. We bear a particular interest in backtrack search algorithms where branches of the exploration tree can be processed in parallel. Profile-based load balancers cannot be applied to them as the computation need only be performed once. It is therefore vital to promptly detect and address load unbalances from the start. A popular solution consists in using the fork/join model. Another approach on which we focus in this article is implemented in the load balancing library of X10. Both of these schemes are sensitive to task granularity. Fined-grained tasks may incur significant overhead, especially with the increased number of parallel workers of many-core architectures, while coarse-grained tasks may cause starvation. Determining a suitable grain size for a particular application is difficult. In this article we present our Java implementation of the X10 load balancing scheme. We extend it with a tuning mechanism which dynamically adjusts the task granularity, increasing the library's versatility and usability. We demonstrate the capabilities of our tuning mechanism to suit many-core clusters using four applications: Unbalanced Tree Search, Pentomino, the Traveling Salesman Problem, and N-Queens. We achieve near identical performance to the ideal fixed grain executions on the first three but suffer from a more significant performance gap on the N-Queens problem. We advance hypotheses as to why.","PeriodicalId":127938,"journal":{"name":"Proceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133567444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Generating energy-efficient code for parallel applications specified by streaming task graphs with dynamic elements 为具有动态元素的流任务图指定的并行应用程序生成高能效代码

Proceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores Pub Date : 2020-02-19 DOI: 10.1145/3380536.3380544

Sebastian Litzinger, J. Keller

{"title":"Generating energy-efficient code for parallel applications specified by streaming task graphs with dynamic elements","authors":"Sebastian Litzinger, J. Keller","doi":"10.1145/3380536.3380544","DOIUrl":"https://doi.org/10.1145/3380536.3380544","url":null,"abstract":"Streaming task graphs are a high-level construct used to specify parallel applications operating on streams of data, and energy-efficient code meeting data throughput requirements can be generated automatically. Tasks can be parallel themselves, so that two levels of parallelism are present. Normally, the task graph structure is assumed to be static, so that static schedulers can be used to map the (parallel) tasks onto a parallel platform to minimize energy consumption for given throughput. We propose a formulation that introduces dynamic elements into the task graph structure, thus allowing to specify applications that can adapt their behavior at runtime, e. g. activating another filter task depending on data quality. This in turn necessitates a runtime system that can re-map tasks in case of a dynamic change of the task structure. We provide the core of such a runtime system together with a task mapper that is able to work incrementally, i. e. that can re-use results from previous mappings when computing a new mapping in case of task addition, change or removal, thus minimizing runtime overhead. We evaluate our prototype implementation with a set of streaming task graphs and compare our results to an optimal static scheduler based on integer linear programming. We find that our prototype is able to meet throughput requirements with < 3.5% energy overhead on average compared to the optimal scheduler.","PeriodicalId":127938,"journal":{"name":"Proceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129390932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Exploring accelerator and parallel graph algorithmic choices for temporal graphs 探索时间图的加速器和并行图算法选择

Proceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores Pub Date : 2020-02-19 DOI: 10.1145/3380536.3380540

Akif Rehman, Masab Ahmad, O. Khan

{"title":"Exploring accelerator and parallel graph algorithmic choices for temporal graphs","authors":"Akif Rehman, Masab Ahmad, O. Khan","doi":"10.1145/3380536.3380540","DOIUrl":"https://doi.org/10.1145/3380536.3380540","url":null,"abstract":"Many real-world systems utilize graphs that are time-varying in nature, where edges appear and disappear with respect to time. Moreover, the weights of different edges are also a function of time. Various conventional graph algorithms, such as single source shortest path (SSSP) have been developed for time-varying graphs. However, these algorithms are sequential in nature and their parallel counterparts are largely overlooked. On the other hand, parallel algorithms for static graphs are implemented as ordered and unordered variants. Unordered implementations do not enforce local or global order for processing tasks in parallel, but incur redundant task processing to converge their solutions. These implementations expose parallelism at the cost of high redundant work. Relax-ordered implementations maintain local order through per-core priority queues to reduce the amount of redundant work, while exposing parallelism. Finally, strict-ordered implementations achieve the work efficiency of sequential version by enforcing a global order at the expense of high thread synchronizations. These parallel implementations are adopted for temporal graphs to explore the choices that provide optimal performance on different parallel accelerators. This work shows that selecting the optimal parallel implementation extracts geometric performance gain of 46.38% on Intel Xeon-40 core and 20.30% on NVidia GTX-1080 GPU. It is also shown that optimal implementation choices for temporal graphs are not always the same as their respective static graphs.","PeriodicalId":127938,"journal":{"name":"Proceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131890925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4