2022 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)最新文献

Accelerating Kernel Ridge Regression with Conjugate Gradient Method for large-scale data using FPGA High-level Synthesis 基于FPGA高级合成的大规模数据共轭梯度加速核脊回归

2022 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) Pub Date : 2022-11-01 DOI: 10.1109/H2RC56700.2022.00009

Yousef Alnaser, Jan Langer, M. Stoll

{"title":"Accelerating Kernel Ridge Regression with Conjugate Gradient Method for large-scale data using FPGA High-level Synthesis","authors":"Yousef Alnaser, Jan Langer, M. Stoll","doi":"10.1109/H2RC56700.2022.00009","DOIUrl":"https://doi.org/10.1109/H2RC56700.2022.00009","url":null,"abstract":"In this work, we accelerate the Kernel Ridge Regression algorithm on an FPGA-based adaptive computing platform to achieve higher performance within faster development time by employing a design approach using high-level synthesis (HLS). We partition the overall algorithm into a quadratic complexity part that runs on the FPGA fabric and a linear complexity part that runs in Python on the ARM processors. In order to avoid storing the potentially huge kernel matrix in external memory, the designed accelerator computes the matrix on-the-fly in each iteration. Moreover, we overcome the memory bandwidth limitation by partitioning the kernel matrix into smaller tiles that are pre-fetched to small local memories and reused multiple times. The design is also parallelized and fully pipelined. The final accelerator can be used for any large-scale data without kernel matrix storage limitations and with an arbitrary number of features. The accelerator reaches 86 GFLOPS on a Kria XCK26 FPGA and 231 GFLOPS on an Alveo U30 card which is within 72% and 90% of the estimated peak performance of those boards. We use the Pynq framework to directly call the accelerator from our Python code. This work is an important first step towards a library for accelerating different Kernel methods for Machine Learning applications for different FPGA platforms that can be used conveniently from Python with a NumPy-like interface.","PeriodicalId":102662,"journal":{"name":"2022 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131283474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Proceedings of H2RC 2022: Eighth International Workshop on Heterogeneous High-Performance Reconfigurable Computing 2022:第八届异构高性能可重构计算国际研讨会

2022 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) Pub Date : 2022-11-01 DOI: 10.1109/h2rc56700.2022.00001

引用次数: 0

A First Step towards Support for MPI Partitioned Communication on SYCL-programmed FPGAs 在sycl编程fpga上支持MPI分区通信的第一步

2022 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) Pub Date : 2022-11-01 DOI: 10.1109/H2RC56700.2022.00007

Steffen Christgau, Marius Knaust, T. Steinke

引用次数: 3

Enabling VirtIO Driver Support on FPGAs 在fpga上启用VirtIO Driver支持

2022 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) Pub Date : 2022-11-01 DOI: 10.1109/H2RC56700.2022.00006

Sahan Bandara, A. Sanaullah, Zaid Tahir, Ulrich Drepper, M. Herbordt

{"title":"Enabling VirtIO Driver Support on FPGAs","authors":"Sahan Bandara, A. Sanaullah, Zaid Tahir, Ulrich Drepper, M. Herbordt","doi":"10.1109/H2RC56700.2022.00006","DOIUrl":"https://doi.org/10.1109/H2RC56700.2022.00006","url":null,"abstract":"Host-FPGA connectivity is critical for enabling a vast number of FPGA use cases in data centers, edge, and IoT. This interface must be reliable, robust, and uniform, whilst supporting necessary protocols and functionality. However, existing support for host-FPGA connectivity has several drawbacks on both the host and the device. This includes a lack of portability and poor upstream support, both of which can make it difficult for CPUs to easily and effectively leverage FPGAs. Native VirtIO drivers in the host operating system can help address some of these limitations, especially on the host side, but implementing device-side support for the VirtIO specification is a challenge due to the substantial hardware complexity involved. In this work, we present a framework for enabling FPGAs to interface native operating system VirtIO drivers on the host. To reduce the implementation overhead and improve portability, this framework uses both generic RTL blocks and modified, chip/device specific PCIe IP blocks. Moreover, this approach implements all the necessary data structures and functionality needed to meet the VirtIO specification requirements. We test the framework using the Xilinx DMA/Bridge Subsystem for PCI Express (XDMA) IP, implemented on an Alinx AX7A200 FPGA board (with a Xilinx XC7A200TFBG484-2 FPGA chip), and a host machine running the Fedora operating system. Our results show that the FPGA can be successfully enumerated as a VirtIO device, and interfaced using only native Linux VirtIO drivers.","PeriodicalId":102662,"journal":{"name":"2022 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132520271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Copyright and Reprint Permissions 版权和转载权限

2022 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) Pub Date : 2022-11-01 DOI: 10.1109/h2rc56700.2022.00002

引用次数: 0

H2RC22 Workshop Organization H2RC22车间组织

2022 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) Pub Date : 2022-11-01 DOI: 10.1109/h2rc56700.2022.00005

引用次数: 0

Fast and energy-efficient derivatives risk analysis: Streaming option Greeks on Xilinx and Intel FPGAs 快速和节能衍生品风险分析:流选项希腊在赛灵思和英特尔fpga

2022 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) Pub Date : 2022-11-01 DOI: 10.1109/H2RC56700.2022.00008

Mark Klaisoongnoen, Nick M. Brown, O. Brown

{"title":"Fast and energy-efficient derivatives risk analysis: Streaming option Greeks on Xilinx and Intel FPGAs","authors":"Mark Klaisoongnoen, Nick M. Brown, O. Brown","doi":"10.1109/H2RC56700.2022.00008","DOIUrl":"https://doi.org/10.1109/H2RC56700.2022.00008","url":null,"abstract":"Whilst FPGAs have enjoyed success in accelerating high-frequency financial workloads for some time, their use for quantitative finance, which is the use of mathematical models to analyse financial markets and securities, has been far more limited to-date. Currently, CPUs are the most common architecture for such workloads, and an important question is whether FPGAs can ameliorate some of the bottlenecks encountered on those architectures. In this paper we extend our previous work accelerating the industry standard Securities Technology Analysis Center's (STAC®) derivatives risk analysis benchmark STAC-A2™, by first porting this from our previous Xilinx implementation to an Intel Stratix-10 FPGA, exploring the challenges encountered when moving from one FPGA architecture to another and suitability of techniques. We then present a host-data-streaming approach that ultimately outperforms our previous version on a Xilinx Alveo U280 FPGA by up to 4.6 times and requiring 9 times less energy at the largest problem size, while outperforming the CPU and GPU versions by up to 8.2 and 5.2 times respectively. The result of this work is a significant enhancement in FPGA performance against the previous version for this industry standard benchmark running on both Xilinx and Intel FPGAs, and furthermore an exploration of optimisation and porting techniques that can be applied to other HPC workloads.","PeriodicalId":102662,"journal":{"name":"2022 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124906213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Message from the H2RC22 Workshop Chairs 来自H2RC22车间主席的消息

2022 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) Pub Date : 2022-11-01 DOI: 10.1109/h2rc56700.2022.00004

引用次数: 0