{"title":"An Efficient Certification Approach for New SN-AG-CU Solder Alloy","authors":"J. Masicat, C. Kumar, M. Nuda","doi":"10.1109/RELPHY.2007.369952","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369952","url":null,"abstract":"This poster presentation showcase the certification methodologies employed for Intel's cellular handheld products in qualifying the Sn-Ag-Cu solder alloy, SAC105, on wire bonded packages. SAC 105 which contains 98.5% tin, 1.0% silver and 0.5% copper was identified as another viable solution to enhance package solder joint reliability performance.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129551371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Leakage Current Characteristic of Pre-Damaged Interlayer Dielectric During Voltage Ramp Method","authors":"Sang-Soo Hwang, Sung-Yup Jung, Young‐Chang Joo","doi":"10.1109/RELPHY.2007.369984","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369984","url":null,"abstract":"In order to investigate the effects of Cu ions migration under BTS, VRDB tests were conducted on the pre-damaged samples. From the various VRDB tests on intrinsic and extrinsic system, migrated Cu ion from electrode plays a role of PF trap site. Since the migration of Cu ions is faster than the formation of intrinsic defects, TTF is set by the migration of Cu ions in extrinsic system.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129956446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Identification of Brittle Solder Joints using High Strain Rate Testing of BGA Solder Joints","authors":"P. Pandher, M. Boureghda","doi":"10.1109/RELPHY.2007.369877","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369877","url":null,"abstract":"With the proliferation of limited life portable electronics the focus of electronics reliability has shifted from long term to short term ruggedness. The probability of a solder joint failing due to mechanical shock is the critical issue. Traditional mechanical reliability testing methods such as three or four point bend tests do not truly recreate the high strain rates experienced in drop shock. New techniques such as high-speed ball pull and high-speed ball shear, impact shear and drop shock are being developed in the industry to test and identify the brittle nature of solder joints and estimate their probability of failure due to mechanical shock. Cookson Electronics has been aggressively developing materials and processes for improved drop shock reliability. In this article we present some of our recent research results on the development of high-speed ball pull testing and success with the technique in differentiating between ductile and brittle solder joints.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129976191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Lue, P. Du, Szu-Yu Wang, E. Lai, K. Hsieh, Rich Liu, Chih-Yuan Lu
{"title":"A Novel Gate-Sensing and Channel-Sensing Transient Analysis Method for Real-Time Monitoring of Charge Vertical Location in Sonos-Type Devices and its Applications in Reliability Studies","authors":"H. Lue, P. Du, Szu-Yu Wang, E. Lai, K. Hsieh, Rich Liu, Chih-Yuan Lu","doi":"10.1109/RELPHY.2007.369889","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369889","url":null,"abstract":"By using poly-gate-sensing in addition to the conventional channel-sensing for Vt (or VFB) presents a novel transient analysis method that is very powerful to monitor the trapped charge vertical location in real time. The sensing in both modes provides two equations that are suitable to solve for two variables - the charge density (Q) and the average charge vertical location (x). Without the second equation (from poly-gate-sensing) Q and x cannot be de-convoluted. The power of this new technique is demonstrated by several examples of reliability studies for SONOS-type devices. The charge trapping efficiency of silicon nitride of different thickness is examined. The charge migration during program/erase cycling and data retention information is observed for the first time using this new tool. The method presented in this work is indeed a powerful tool for detailed understanding of trapping dynamics.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"101-B 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131042049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reconsideration of Hydrogen-Related Degradation Mechanism in Gate Oxide","authors":"Y. Mitani, T. Yamaguchi, H. Satake, A. Toriumi","doi":"10.1109/RELPHY.2007.369896","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369896","url":null,"abstract":"In this paper, we have investigated the correlation between released hydrogen from Si/SiO2 interface and trap creation in bulk SiO2. The key point of these experiments is that hydrogen release from the interface is performed without trap creation in bulk SiO2 by injected hot carriers. Therefore, negative bias temperature (NBT) stress or substrate hot electron (SHE) stress was utilized to release hydrogen from Si/SiO2 interface. As a result, SILC is clearly observed after low voltage NBT stress in pMOSFETs. In this stress condition, impact ionization at anode interface due to injected hot electrons was negligible. In the same way, SILC is also observed by applying SHE stress in nMOSFETs. In addition, the SILC is suppressed by decreasing released hydrogen using fluorine incorporation in both stress conditions. From these results, we inferred that the released hydrogen from Si/SiO2 interface strongly correlates to the trap creation in gate oxides","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126883879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Photo Misalignment Impact on the Hot Carrier Reliability of Lateral DMOS Devices","authors":"D. Brisbin, P. Lindorfer, P. Chaparala","doi":"10.1109/RELPHY.2007.369941","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369941","url":null,"abstract":"Power management devices often require operation in the 20 V to 30 V range. A common choice for the power MOS driver is an n-channel lateral DMOS (N-LDMOS) device. An advantage of N-LDMOS device is that it can easily be integrated within existing technologies to handle a wide range of operating voltages without significant process changes. Because of the high voltages applied to the N-LDMOS device hot carrier (HC) degradation is a real reliability concern. In high power applications N-LDMOS devices are often implemented in transistor arrays where the basic cell is a dual gate single drain device. This paper focuses on understanding unusual N-LDMOS HC results in which single gate devices had significantly better HC performance than dual gate devices.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"383 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123347617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Quantitative Analysis of Neutron-Induced Multi-Cell Upset in Deep Submicron SRAMs and of the Impact Due to Anomalous Noise","authors":"H. Kameyama, Y. Yahagi, E. Ibe","doi":"10.1109/RELPHY.2007.369566","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369566","url":null,"abstract":"In this work, the multiplicity of neutron-induced upsets of SRAMs with 130/180 nm technologies is analyzed by using several neutron beams and RTSER. The neutron peak-energy dependence of the ratio for MCU to the total number of upsets can be described by Weibull-type function with a threshold energy for the MCU. As a result of the 130nm SRAM test, the probability function of MCU can be approximated as a superposition of an exponential and a Lorentzian. We also demonstrate that the MCU/SEU ratio obtained by real-time measurements (RTSER) cross over the ASER data at around 20-40MeV. This indicates that the MCU obtained from ASER test using high neutron peak energy more than 50MeV tends to lead to an excessive estimation of the MCU/SEU ratio compared to the RTSER measurements. In addition, the effect due to anomalous noise has been studied and the phenomenon could be suggested as some special signs related to a geophysical mechanism and is expected to be investigated further with more analysis.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126405268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Parthasarathy, M. Denais, V. Huard, C. Guérin, G. Ribes, E. Vincent, A. Bravaix
{"title":"Unified Perspective of NBTI and Hot-Carrier Degradation in CMOS using on-the-Fly Bias Patterns","authors":"C. Parthasarathy, M. Denais, V. Huard, C. Guérin, G. Ribes, E. Vincent, A. Bravaix","doi":"10.1109/RELPHY.2007.369575","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369575","url":null,"abstract":"This work views NBTI and various conditions of channel hot carrier (CHC) degradation in PMOS and NMOS devices from a unified perspective. This is accomplished by a novel technique using sequential application of stress biases and monitoring the degradation on-the-fly. Thereby, we are able to observe and segregate the distinct mechanisms co-existing during a particular condition of degradation. In particular, we gain critical insights into recovery phenomena, which are observed during certain conditions of CHC degradation (Mistry et al., 1991) as well as during NBTI (Rangan, 2003). These findings set the stage for consistent physical models for degradation as well as for design simulation under multiple operating modes","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121484505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improved Hot Carrier Reliability in Strained-Channel NMOSFETS with TEOS Buffer Layer","authors":"Ching-Sen Lu, Horng-Chih Lin, Yao-Jen Lee, Tiao-Yuan Huang","doi":"10.1109/RELPHY.2007.369562","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369562","url":null,"abstract":"Both the presence of the SiN capping layer and the deposition process itself exert significant impacts on the device operation and the associated reliability characteristics. The accompanying bandgap narrowing, increased carrier mobility and hydrogen diffusion from the SiN capping process tend to worsen the hot-electron reliability. This work shows that, owing to the use of hydrogen-containing precursors, abundant hydrogen species is presumably incorporated in the oxide and may contribute to the hot-electron degradation, even if the SiN layer is removed later and the channel strain is relieved. Furthermore, by blocking the diffusion of hydrogen species, the devices with 20nm-thick TEOS buffer layer can effectively improve the hot-electron reliability without compromising the performance enhancement by the strain induced by the SiN capping. Optimization of both the thickness of buffer layer and SiN deposition process are thus essential to the implementation of the uniaxial strain in NMOS devices.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"383 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125104217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Kang, Sungnam Chang, S. Seo, Yongwook Song, H. Yoon, Eunjung Lee, D. Chang, Wonseong Lee, Byung-Gook Park, J. Lee, I. Park, Sangwoo Kang, Hyungcheol Shin
{"title":"Improving the Endurance Characteristics Through Boron Implant at Active Edge in 1 G NAND Flash","authors":"D. Kang, Sungnam Chang, S. Seo, Yongwook Song, H. Yoon, Eunjung Lee, D. Chang, Wonseong Lee, Byung-Gook Park, J. Lee, I. Park, Sangwoo Kang, Hyungcheol Shin","doi":"10.1109/RELPHY.2007.369996","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369996","url":null,"abstract":"One of the most important issues of NAND flash memory is reliability problems caused by oxide and interface traps. But it has been revealed that their generation rate increases by Fowler-Nordheim current stressing on the tunnel oxide as the channel width of shallow trench isolation (STI) isolated NAND flash cells shrinks and electric field is increased at active edge of STI profile. By adjusting the boron doping of active edge, we decrease not only the electric field but also the trap generation. Also we confirmed the improvement of endurance and bake retention characteristics.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121767134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}