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2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)最新文献

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A Normalized Filtered-x Generalized Fractional Lower Order Moment Adaptive Algorithm for Impulsive ANC Systems 脉冲ANC系统的归一化滤波-x广义分数阶矩自适应算法
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8623904
M. Akhtar
{"title":"A Normalized Filtered-x Generalized Fractional Lower Order Moment Adaptive Algorithm for Impulsive ANC Systems","authors":"M. Akhtar","doi":"10.1109/MWSCAS.2018.8623904","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8623904","url":null,"abstract":"This paper proposes an efficient algorithm for impulsive active noise control (IANC) systems. The impulsive sources cannot be modeled by Gaussian distribution, and hence the standard adaptive algorithm based on second order statistics would give poor performance or even fail to converge. One solution is to derive adaptive algorithm by minimizing a fractional low order moment, resulting in the famous filtered-x least mean p-power (FxLMP) algorithm. The proposed algorithm discussed in this paper is based on a previously proposed generalized FxLMP algorithm. The key idea here is to introduce a variable step-size using a convex-combination approach. A large value is used at the start-up of IANC system to achieve a fast convergence speed. As the AINC system converges, the step-size automatically reduces to a small value to improve the steady-state noise reduction performance. Simulations demonstrate the effectiveness of the proposed algorithm.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114416518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Gaussian Process Regression for Improving the Performance of Self-powered Time-of-Occurrence Sensors 高斯过程回归提高自供电发生时间传感器性能
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8624046
Liang Zhou, K. Aono, S. Chakrabartty
{"title":"Gaussian Process Regression for Improving the Performance of Self-powered Time-of-Occurrence Sensors","authors":"Liang Zhou, K. Aono, S. Chakrabartty","doi":"10.1109/MWSCAS.2018.8624046","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8624046","url":null,"abstract":"In our previous work, we had demonstrated a CMOS timer-injector integrated circuit for self-powered sensing of time-of-occurrence of mechanical events. While the sensor could achieve an improved time-stamping accuracy by averaging the output across over multiple channels, the mismatch between the channels made the calibration process cumbersome and time-consuming. In this paper, we propose the use of non-parametric machine learning techniques to achieve more robust and accurate event reconstruction. This is demonstrated using training and testing data that were obtained from fabricated prototypes on a $0.5-mu mathrm {m}$ CMOS process; the model trained using Gaussian process regression can achieve an average recovery accuracy of 3.3% on testing data, which is comparable to the performance of using an averaging technique on calibrated injection results. The experimental results also validate that scalable performance can be achieved by employing more injection channels.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114463447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Comparative Study Of Injection Locked Frequency Divider Using Harmonic Mixer In Weak And Strong Inversion 弱反转与强反转中谐波混频器注入锁定分频器的比较研究
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8623850
Yushi Zhou, J. Mercier, F. Yuan
{"title":"A Comparative Study Of Injection Locked Frequency Divider Using Harmonic Mixer In Weak And Strong Inversion","authors":"Yushi Zhou, J. Mercier, F. Yuan","doi":"10.1109/MWSCAS.2018.8623850","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8623850","url":null,"abstract":"This paper presents a comparative study of a divide-by-4 injection locked frequency divider with the injection transistor operating in both the weak and strong inversion regions. The relation between the maximum lock range of the frequency divider and the nonlinearity of the injection transistor is investigated. We show that the strong nonlinear characteristics of the injection transistor induce the wider lock range. We further investigate the existence of the optimum biasing point in the weak inversion region, which leads to the maximum lock range given the same injection power. The injection locked frequency divider designed in GF 130 nm 1.2 V CMOS technology, is validated using the simulation results.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114586528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Hardware Trojan Based Security Issues in Home Area Network: A Testbed Setup 基于硬件木马的家庭局域网安全问题:一个试验台设置
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8624048
Hawzhin Mohammed, Jimmy Howell, S. R. Hasan, N. Guo, Faiq Khalid, O. Elkeelany
{"title":"Hardware Trojan Based Security Issues in Home Area Network: A Testbed Setup","authors":"Hawzhin Mohammed, Jimmy Howell, S. R. Hasan, N. Guo, Faiq Khalid, O. Elkeelany","doi":"10.1109/MWSCAS.2018.8624048","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8624048","url":null,"abstract":"Advanced Metering Infrastructure (AMI) is the main player in todays Smart Grid, and Home Area Network (HAN) is an important subsystem in AMI. HAN connects the smart home appliances (SHA) inside the home to the smart meter (SM), which is connected to the power utility company. In the last decade, hardware Trojans (HT), have been extensively studied in both academia and industry. Consequently, the vulnerability of integrated circuits (ICs) against HTs leads to the potential security threat to any system that contains ICs, and HAN is no exception. However, to the best of authors knowledge, the potential effect of HTs on HAN has not been studied in the literature so far. In this paper, we are investigating HT in HAN network. In the process, we developed a testbed which can be scalable up to 127 nodes using I2C interface to control and implement any kind of required network behavior. We introduced three possible scenarios of HTs in this HAN network testbed. These scenarios illustrate the manifestation of HTs in the HAN that leads to network performance degradation.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121974943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimizing the Inductance Time-Constant Ratio of Polygonal Integrated Inductors 优化多边形集成电感的电感时间常数比
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8623945
Ahmed H. Shaltout, S. Gregori
{"title":"Optimizing the Inductance Time-Constant Ratio of Polygonal Integrated Inductors","authors":"Ahmed H. Shaltout, S. Gregori","doi":"10.1109/MWSCAS.2018.8623945","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8623945","url":null,"abstract":"This paper optimizes the inductance time-constant ratio of integrated inductors in order to improve the energy conversion efficiency of fully-integrated power converters. An inductance model is proposed and all the self and mutual partial inductances between segments are calculated. Multiple inductors were designed and simulated in TSMC 65-nm technology to validate the analytical model and the simulation results show a good agreement with the analysis.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116819812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Ternary Device using Graphene Memcapacitor for Post Binary Era 后二元时代用石墨烯mem电容器的三元器件
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8624098
J. A. Patel, Zarin Tasnim Sandhie, M. Chowdhury
{"title":"Ternary Device using Graphene Memcapacitor for Post Binary Era","authors":"J. A. Patel, Zarin Tasnim Sandhie, M. Chowdhury","doi":"10.1109/MWSCAS.2018.8624098","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8624098","url":null,"abstract":"Ternary logic devices are expected to lead to an exponential increase of the information handling capability, which binary logic cannot support. Memcapacitor is an emerging device that exhibits hysteresis behavior, which can be manipulated by external parameters, such as, the applied electric field or voltage. One of the unique properties of the memcapacitor is that by using the percolation approach, we can achieve Metal-Insulator-Transition (MIT) phenomenon, which can be utilized to obtain a staggered hysteresis loop. For multivalued logic devices staggered hysteresis behavior is the critical requirement. In this paper, we propose a new conceptual design of a ternary logic device by vertically stacking dielectric material interleaved with layers of graphene nanoribbon (GNR) between the two external metal plates. The proposed device structure displays the memcapacitive behavior with the fast switching metal-to-insulator transition in picosecond scale. The device model is later extended into a vertical-cascaded version, which performs as a ternary device.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129945523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Correlation-Based Cryptanalysis of a Ring Oscillator Based Random Number Generator 基于环形振荡器的随机数发生器的相关密码分析
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8624064
Burak Acar, Salih Ergun
{"title":"Correlation-Based Cryptanalysis of a Ring Oscillator Based Random Number Generator","authors":"Burak Acar, Salih Ergun","doi":"10.1109/MWSCAS.2018.8624064","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8624064","url":null,"abstract":"Random Number Generators (RNGs) are crucial for many security applications for generating unpredictable bit streams. Fully digital Random Number Generators which are implemented in FPGA platforms are usually preferred for their high-speed availability and their ease of integration to digital platforms. On the other hand, attention should be paid while placing and routing ring oscillators as much as possible. This paper presents an implementation of a Random Number Generator based on ring oscillators on FPGA and the cryptanalysis of it via correlation analysis. The main aim of this paper is to analyze the correlation between the output bit streams produced by the RNG and the attack circuit coupled to the main circuit. In the main RNG circuit, all ring oscillators are placed far from each other to obtain independent random bit streams at the output. Experimental results show that the effective correlation between RNG and attack circuit can be obtained due to coupling.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129946145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
On-chip Impedance Evaluation with Auto-calibration based on Auto-balancing Bridge 基于自动平衡桥的片上阻抗自动校准评估
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8623881
Takaaki Shirakawa, Ryosuke Sakai, S. Nakatake
{"title":"On-chip Impedance Evaluation with Auto-calibration based on Auto-balancing Bridge","authors":"Takaaki Shirakawa, Ryosuke Sakai, S. Nakatake","doi":"10.1109/MWSCAS.2018.8623881","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8623881","url":null,"abstract":"We propose a circuit mechanism with an autocalibration in the impedance measurement circuit based on the auto-balancing bridge method. In the auto-balancing bridge method, an inverting amplifier circuit using an operational amplifier is used. Since the measurement accuracy depends on the feedback resistance of the inverting amplifier circuit, it is necessary to replace the feedback resistor each time as checking the measured value of the resistance of the DUT (device-undertest) so as to match the value. In this work, by employing a current-type D/A converter as a feedback resistor, we design a circuit with calibration of the resistance value and attain highly accurate measurement by simulation.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128385886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Ultra low-energy active charge restoration DAC for SAR Analog-to-Digital Converter 用于SAR模数转换器的超低能量有电荷恢复DAC
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8623977
Japesh Vohra, V. Hande
{"title":"Ultra low-energy active charge restoration DAC for SAR Analog-to-Digital Converter","authors":"Japesh Vohra, V. Hande","doi":"10.1109/MWSCAS.2018.8623977","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8623977","url":null,"abstract":"A novel architecture for Digital-to-Analog converter (DAC) used in successive approximation register Analog-to-Digital converters (SAR ADCs) is proposed. It reduces the energy consumption as well as required on-chip capacitor area. A single unit capacitor section using charge from a previously charged capacitor is added to the circuit in series after every comparison and any charge lost is partially restored. Using a single capacitor and charge sharing method reduces the energy consumption for capacitor switching, capacitor area and total capacitance to a small fraction of the conventional SAR ADC.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129267942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A balanced hybrid ring oscillator for precise temperature compensation 用于精确温度补偿的平衡混合环振荡器
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2018-08-01 DOI: 10.1109/MWSCAS.2018.8623996
Kanglin Xiao, Bo Wang, Xiaoqi Lin, Changpei Qiu
{"title":"A balanced hybrid ring oscillator for precise temperature compensation","authors":"Kanglin Xiao, Bo Wang, Xiaoqi Lin, Changpei Qiu","doi":"10.1109/MWSCAS.2018.8623996","DOIUrl":"https://doi.org/10.1109/MWSCAS.2018.8623996","url":null,"abstract":"A balanced hybrid ring oscillator (RO) is proposed in this paper for the precise temperature compensation. Different from the previous ROs with only one type of delay cell, the proposed RO consists of both the delay cells with PTAT (proportional to the absolute temperature) characteristics and those with CTAT (complementary to absolute temperature) characteristics. The optimal temperature compensated point can then be found by adjusting the number of PTAT and CTAT delay cells and the load capacitance of each delay cell. Both ideal and non-ideal models are developed to explain this temperature compensation mechanism. Finally, combining the opposite temperature characteristics of normal RO and current-starved RO, a 13.4 MHz on-chip clock circuit is implemented in 0.13um CMOS process, with 14.6 ppm/°C over the temperature range from -40°C to 80°C. The worst process variation is 1.19% and the supply variation is 0.06%/V.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127015683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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