{"title":"用于精确温度补偿的平衡混合环振荡器","authors":"Kanglin Xiao, Bo Wang, Xiaoqi Lin, Changpei Qiu","doi":"10.1109/MWSCAS.2018.8623996","DOIUrl":null,"url":null,"abstract":"A balanced hybrid ring oscillator (RO) is proposed in this paper for the precise temperature compensation. Different from the previous ROs with only one type of delay cell, the proposed RO consists of both the delay cells with PTAT (proportional to the absolute temperature) characteristics and those with CTAT (complementary to absolute temperature) characteristics. The optimal temperature compensated point can then be found by adjusting the number of PTAT and CTAT delay cells and the load capacitance of each delay cell. Both ideal and non-ideal models are developed to explain this temperature compensation mechanism. Finally, combining the opposite temperature characteristics of normal RO and current-starved RO, a 13.4 MHz on-chip clock circuit is implemented in 0.13um CMOS process, with 14.6 ppm/°C over the temperature range from -40°C to 80°C. The worst process variation is 1.19% and the supply variation is 0.06%/V.","PeriodicalId":365263,"journal":{"name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A balanced hybrid ring oscillator for precise temperature compensation\",\"authors\":\"Kanglin Xiao, Bo Wang, Xiaoqi Lin, Changpei Qiu\",\"doi\":\"10.1109/MWSCAS.2018.8623996\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A balanced hybrid ring oscillator (RO) is proposed in this paper for the precise temperature compensation. Different from the previous ROs with only one type of delay cell, the proposed RO consists of both the delay cells with PTAT (proportional to the absolute temperature) characteristics and those with CTAT (complementary to absolute temperature) characteristics. The optimal temperature compensated point can then be found by adjusting the number of PTAT and CTAT delay cells and the load capacitance of each delay cell. Both ideal and non-ideal models are developed to explain this temperature compensation mechanism. Finally, combining the opposite temperature characteristics of normal RO and current-starved RO, a 13.4 MHz on-chip clock circuit is implemented in 0.13um CMOS process, with 14.6 ppm/°C over the temperature range from -40°C to 80°C. The worst process variation is 1.19% and the supply variation is 0.06%/V.\",\"PeriodicalId\":365263,\"journal\":{\"name\":\"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"volume\":\"73 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2018.8623996\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2018.8623996","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A balanced hybrid ring oscillator for precise temperature compensation
A balanced hybrid ring oscillator (RO) is proposed in this paper for the precise temperature compensation. Different from the previous ROs with only one type of delay cell, the proposed RO consists of both the delay cells with PTAT (proportional to the absolute temperature) characteristics and those with CTAT (complementary to absolute temperature) characteristics. The optimal temperature compensated point can then be found by adjusting the number of PTAT and CTAT delay cells and the load capacitance of each delay cell. Both ideal and non-ideal models are developed to explain this temperature compensation mechanism. Finally, combining the opposite temperature characteristics of normal RO and current-starved RO, a 13.4 MHz on-chip clock circuit is implemented in 0.13um CMOS process, with 14.6 ppm/°C over the temperature range from -40°C to 80°C. The worst process variation is 1.19% and the supply variation is 0.06%/V.