S. Palanisamy, J. Lutz, R. Boldyrjew-Mast, T. Basler
{"title":"Thermomechanical behaviour of inverse diode in SiC MOSFETs under surge current stress","authors":"S. Palanisamy, J. Lutz, R. Boldyrjew-Mast, T. Basler","doi":"10.1109/IRPS45951.2020.9129286","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129286","url":null,"abstract":"In this work, thermomechanical failures during single and repetitive surge current events of 40 mΩ class, 1.2 kV SiC MOSFET inverse diodes were investigated. The single event surge current was performed under different pulse length in channel-off mode. It was observed that the body diode survived 10 ms surge currents more than 11 times the application-near nominal current of 20 A. After surge current destruction a failure analysis was performed. At a high surge current event (232 A) the device failed due to the very high temperature, the aluminium metallization was melted around the bond foot and the melted metallization shorted gate and source (GS) metal. In addition to that, repetitive surge current tests, high temperature reverse bias (HTRB) tests under negative gate bias and high temperature gate bias test (HTGB) with samples exposed to repetitive surge current were performed to investigate different aging mechanisms to determine reliability aspects of the inverse diode in SiC MOSFETs.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132439486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Comparison of variability of HCI induced drift for SiON and HKMG devices","authors":"X. Federspiel, C. Diouf, F. Cacho, E. Vincent","doi":"10.1109/IRPS45951.2020.9128326","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128326","url":null,"abstract":"we present here a detailed comparison of HCI induced drift of logic devices parameters from 40nm SiON and 28nm HKMG nodes. Repeated HCI stress with sampling ranging from 70 to 200 allow a comparison of Vth drift Idlin drift variability through various HCI Stress configurations.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130917503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. P. Kozak, Ruizhe Zhang, Jingcun Liu, K. Ngo, Yuhao Zhang
{"title":"Physics of Degradation in SiC MOSFETs Stressed by Overvoltage and Overcurrent Switching","authors":"J. P. Kozak, Ruizhe Zhang, Jingcun Liu, K. Ngo, Yuhao Zhang","doi":"10.1109/IRPS45951.2020.9128330","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128330","url":null,"abstract":"This work presents the ruggedness of SiC power MOSFETs outside the safe-operating-area (SOA) conditions based on a hard-switching cycling test. The device was stressed to withstand overvoltage and overcurrent beyond their voltage and current ratings in each switching cycle. This switching cycling test was performed at an ambient temperature of 25 oC and 100 oC. Two independent degradations, one at the gate-oxide and the other at the semiconductor junction region, were observed. The second degradation has not been previously reported in the literature. Both degradations were found to accelerate at the high ambient temperature. The physics of these two device degradations were unveiled: the hot-electron induced gate-oxide degradation accounts for the first device degradation; the electron hopping through the defect states created in the stress tests accounts for the second device degradation.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128795683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Heung-Kook Ko, Sena Park, Jihyun Ryu, Sung Ryul Kim, G. Lee, Dongjoon Lee, S. Pae, Euncheol Lee, Yongsung Ji, Hai Jiang, T. Jeong, T. Uemura, Dongkyun Kwon, Hyungrok Do, Hyungu Kahng, Y. Cho, Jiyoon Lee, Seoung Bum Kim
{"title":"Early Diagnosis and Prediction of Wafer Quality Using Machine Learning on sub-10nm Logic Technology","authors":"Heung-Kook Ko, Sena Park, Jihyun Ryu, Sung Ryul Kim, G. Lee, Dongjoon Lee, S. Pae, Euncheol Lee, Yongsung Ji, Hai Jiang, T. Jeong, T. Uemura, Dongkyun Kwon, Hyungrok Do, Hyungu Kahng, Y. Cho, Jiyoon Lee, Seoung Bum Kim","doi":"10.1109/IRPS45951.2020.9128932","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128932","url":null,"abstract":"This paper proposes to use machine learning (ML) methods to predict wafer quality using Fab inline measured items, DC measurements, and DVS (Dynamic Voltage Stress) at wafer sort. With developed ML approach, the predicted accuracy is more than 80% in 8 nm products used in this study. We believe this method can be further fine-tuned to help enable ICs at the high level expected for automotive systems. By assigning predictive rankings, the method also helps enable best tooling system for higher quality","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125592766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Jeong, Miji Lee, Yunkyung Jo, Jinwoo Kim, Min Kim, M. Yeo, Jinseok Kim, Hyunjun Choi, Joosung Kim, Yoojin Jo, Yongsung Ji, T. Uemura, Hai Jiang, Dongkyun Kwon, H. Rhee, S. Pae, Brandon Lee
{"title":"Reliability on EUV Interconnect Technology for 7nm and beyond","authors":"T. Jeong, Miji Lee, Yunkyung Jo, Jinwoo Kim, Min Kim, M. Yeo, Jinseok Kim, Hyunjun Choi, Joosung Kim, Yoojin Jo, Yongsung Ji, T. Uemura, Hai Jiang, Dongkyun Kwon, H. Rhee, S. Pae, Brandon Lee","doi":"10.1109/IRPS45951.2020.9129318","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129318","url":null,"abstract":"In this research, we present the robust reliability performance of BEOL by utilizing EUV single patterning and further feasibility of EUV process for future nodes. As compared to ArF, EUV BEOL shows superior reliability performances such as significantly improved TDDB, breakdown voltage (Vbd), robust resistance shift with SM and TC tests and reliable package level characteristics. Long-term TDDB analysis follows an even more aggressive power law model rather than the root E model under low bias. Newly developed via array (quasi-power rail) EM structure has a great feasibility to enhance EM performance for future nodes.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126796367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Over-Voltage Protection on the CC Pin of USB Type-C Interface against Electrical Overstress Events","authors":"Chao-Yang Ke, M. Ker","doi":"10.1109/IRPS45951.2020.9129160","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129160","url":null,"abstract":"In USB type-C interface, owing to the shrinking space between the pins of connector and the required high-power delivery, the electrical overstress (EOS) events due to some pins shorting to VBUS pin during plugging or unplugging operations had been reported. In this work, an over voltage protection (OVP) design on the CC pin of USB type-C IC was proposed, where a HVNMOS as a pass transistor was used to avoid the CC pin from EOS. An EOS detection circuit is proposed to turn off the gate of the HVNMOS when EOS stressing on the CC pin, which can mitigate the hot carrier degradation (HCD) of HVNMOS. Silicon chip fabricated in a 0.15-μm BCD technology has been measured to successfully verify the proposed OVP design in device level and circuit level.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125922708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Sutaria, Jihan Standfest, I. Meric, A. Davoody, S. Namalapuri, Trinadh Mutyala, P. Supriya, B. Gill, S. Ramey, Jeffery Hicks
{"title":"Novel Re-configurable Circuits For Aging Characterization: Connecting Devices to Circuits","authors":"K. Sutaria, Jihan Standfest, I. Meric, A. Davoody, S. Namalapuri, Trinadh Mutyala, P. Supriya, B. Gill, S. Ramey, Jeffery Hicks","doi":"10.1109/IRPS45951.2020.9128347","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128347","url":null,"abstract":"Circuit reliability is a significant concern in scaled technologies. Physical aging models derived by DC stress on discrete devices are accurate to an extent, but can be further improved by evaluating the behaviour of simple circuits such as ring oscillators (RO). In this work, we establish correlation between individual device degradation to circuit’s figure of merit (frequency degradation) to refine understanding of the predictive ability of DC models. We further present novel re-configurable circuits that enables different waveform scenarios seen in design to bridge gaps between DC-stressed device aging and complex circuits. Unique features of this work include: (1) Correlating discrete device degradation to circuit performance degradation, (2) development of a novel PMOS/NMOS aging isolator circuit (PNI) which can isolate the aging contribution of a single device type, and (3) development of a state-of-art re-configurable circuit that modulate waveforms to customize the aging contribution from any particular physical mechanism (NBTI, PBTI, N-HCI or P-HCI).","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116614163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Gao, M. Mehedi, Haibao Chen, Xinsheng Wang, Jianfu Zhang, Xiaoling Lin, Zhiyuan He, Yiqiang Chen, Dengyun Lei, Yun Huang, Yunfei En, Zhigang Ji, Runsheng Wang
{"title":"A fast and test-proven methodology of assessing RTN/fluctuation on deeply scaled nano pMOSFETs","authors":"R. Gao, M. Mehedi, Haibao Chen, Xinsheng Wang, Jianfu Zhang, Xiaoling Lin, Zhiyuan He, Yiqiang Chen, Dengyun Lei, Yun Huang, Yunfei En, Zhigang Ji, Runsheng Wang","doi":"10.1109/IRPS45951.2020.9129230","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129230","url":null,"abstract":"Random Telegraph Noise (RTN)/fluctuation is one of the most serious reliability issues in modern deeply scaled CMOS. The current RTN characterization methods need to select devices and can only capture the fast traps, thus it is very difficult to predict and validate device long-term fluctuation behavior. A new fast and test-proven methodology of assessing RTN/fluctuation is proposed in this work. By using the Within Device Fluctuation (WDF), all the devices’ fluctuation can be captured. Moreover, WDF can be well explained and simulated as a sum of all the As-grown Traps (AT) induced RTN.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121807532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}