2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)最新文献

Approximate Divider Design Based on Counting-Based Stochastic Computing Division 基于计数随机计算除法的近似除法设计

2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD) Pub Date : 2021-08-30 DOI: 10.1109/MLCAD52597.2021.9531079

Shuyuan Yu, Yibo Liu, S. Tan

{"title":"Approximate Divider Design Based on Counting-Based Stochastic Computing Division","authors":"Shuyuan Yu, Yibo Liu, S. Tan","doi":"10.1109/MLCAD52597.2021.9531079","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531079","url":null,"abstract":"Stochastic computing (SC) promises extremely low cost and energy efficiency for error-tolerant arithmetic operations in many emerging applications such as image processing and deep neural networks. Existing SC-based nonlinear functions like division, however, require highly correlated bit-streams, which does not fit well with the existing SC computing framework in which randomness is required for accuracy. In this paper, we propose a novel SC-based divider design based on recently proposed counting-based stochastic computing scheme, which is much more accurate and faster than traditional SC, and does not depend on randomness of bit-streams for accuracy. We show how such counting-based SC can be applied to nonlinear functions like division. The new divider, called counting-based divider, or CBDIV, exploits both the correlation requirement of existing SC-based division methods and high efficiency of counting-based SC scheme. It essentially combines the best of two worlds in SC and the resulting division operation can be performed as a more efficient partial counting process. Experimental results show that the proposed CBDIV implemented in a 32nm technology node outperforms state of art works by 77.8% in accuracy, 37.1% in delay, 21.5% in area, 50.6% in ADP (area delay product) and 25.9% in power. CBDIV also saves 31.9% in energy consumption when compared to the fixed-point division baseline, and is much more energy efficient than existing SC-based dividers for binary inputs and outputs required in efficient image process implementations. Furthermore, CBDIV with 5-bit precision can even outperform state of art works with 7-bit precision in accuracy by 15.4%. Finally, we compare CBDIV with other state of art SC dividers in contrast stretch application and show that CBDIV can improve the accuracy with 20.6dB in average, which is a huge improvement.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114945618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Connectivity-Based Machine Learning Compact Models for Interconnect Parasitic Capacitances 互连寄生电容的基于连通性的机器学习紧凑模型

2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD) Pub Date : 2021-08-30 DOI: 10.1109/MLCAD52597.2021.9531300

Mohamed Saleh Abouelyazid, S. Hammouda, Y. Ismail

{"title":"Connectivity-Based Machine Learning Compact Models for Interconnect Parasitic Capacitances","authors":"Mohamed Saleh Abouelyazid, S. Hammouda, Y. Ismail","doi":"10.1109/MLCAD52597.2021.9531300","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531300","url":null,"abstract":"A novel neural-networks parasitic extraction modeling methodology for interconnect parasitic capacitances is developed in rule-based extractors. The current rule-based extractors rely on thousands of parasitic capacitance formulas, each covering few or very limited set of interconnect patterns. These formulas also typically suffer from large errors in corner cases. The proposed methodology provides compact cross-section neural-network models that predict parasitic coupling capacitances for many diverse metal arrangements considering metals connectivity. These models significantly improve the accuracy of rule-based extraction methods. Also, they significantly reduce the pattern mismatches in traditional rule-based methods. The inputs to the proposed compact models are: dimensions of a layout pattern, aggressor polygons, and the required victim polygons for a certain process stack. Two different pattern representations are proposed to be used as inputs to neural-networks models: ratio-based and dimensions-based representations. The proposed methodology shows superior characteristics as compared to traditional existing models in four ways. First, it has high pattern coverage. Second, it mitigates the pattern mismatches. Third, it provides compact, descriptive, and accurate cross-section parasitic models. Fourth, it can handle the increasing accuracy requirements in advanced nodes. The proposed methodology is tested over three test chips of 28nm process node with more than 4.8M interconnect structures. The proposed methodology managed to significantly reduce the pattern mismatches and provided outstanding results as compared to field-solvers with an average error < 0.1% and a standard deviation < 3.2%.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134154230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Neural Networks for Transient Modeling of Circuits : Invited Paper 电路暂态建模的神经网络:特邀论文

2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD) Pub Date : 2021-08-30 DOI: 10.1109/MLCAD52597.2021.9531153

J. Xiong, Alan Yang, M. Raginsky, E. Rosenbaum

引用次数: 4

Fast and Accurate PPA Modeling with Transfer Learning 快速和准确的PPA建模与迁移学习

2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD) Pub Date : 2021-08-30 DOI: 10.1109/MLCAD52597.2021.9531109

Luis Francisco, P. Franzon, W. R. Davis

引用次数: 3

Variation-aware Analog Circuit Sizing with Classifier Chains 基于分类器链的变化感知模拟电路尺寸

2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD) Pub Date : 2021-08-30 DOI: 10.1109/MLCAD52597.2021.9531273

Zhengfeng Wu, I. Savidis

{"title":"Variation-aware Analog Circuit Sizing with Classifier Chains","authors":"Zhengfeng Wu, I. Savidis","doi":"10.1109/MLCAD52597.2021.9531273","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531273","url":null,"abstract":"In this work, a simulation-based optimization framework is proposed that determines the sizing of components of an analog circuit to meet target design specifications while also satisfying the robustness specifications set by the designer. The robustness is guaranteed by setting a limit on the standard deviations of the variations in the performance parameters of a circuit across all process and temperature corners of interest. Classifier chains are utilized that, in addition to modeling the relationship between inputs and outputs, learn the relationships among output labels. Additional design knowledge is inferred from the optimal ordering of the classifier chain. A case study is provided, where an LNA is designed in a 65 nm fabrication process. The corners of interest include the combination of the three temperatures of 20°C, 80°C, and 120°C, and the five process corners of typical-typical, slow-slow, fast-fast, slow-fast, and fast-slow. The adoption of classifier chains and the ensemble of classifier chains provides an improvement in the prediction accuracy as compared to the utilization of binary relevance. A qualified design solution is generated that satisfies both the performance and robustness specifications within 5 executed iterations of the design loop.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122691208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Fast Electrostatic Analysis For VLSI Aging based on Generative Learning 基于生成学习的VLSI老化快速静电分析

2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD) Pub Date : 2021-08-30 DOI: 10.1109/MLCAD52597.2021.9531320

Subed Lamichhane, Shaoyi Peng, Wentian Jin, S. Tan

引用次数: 1

Effective Machine-Learning Models for Predicting Routability During FPGA Placement 预测FPGA放置可达性的有效机器学习模型

2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD) Pub Date : 2021-08-30 DOI: 10.1109/MLCAD52597.2021.9531243

T. Martin, S. Areibi, G. Grewal

引用次数: 4

An Efficient Timing Model of Flip-Flops Based on Artificial Neural Network 基于人工神经网络的触发器有效定时模型

2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD) Pub Date : 2021-08-30 DOI: 10.1109/MLCAD52597.2021.9531284

Madhvi Agarwal, Sneh Saurabh

{"title":"An Efficient Timing Model of Flip-Flops Based on Artificial Neural Network","authors":"Madhvi Agarwal, Sneh Saurabh","doi":"10.1109/MLCAD52597.2021.9531284","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531284","url":null,"abstract":"Traditionally, the timing model of a flip-flop in the technology libraries captures the setup time (ST), hold time (HT) and clock-to-q (C2Q) delays in separate two-dimensional lookup tables. However, it is well-known that these attributes of flip-flops are interdependent. By modeling them separately we introduce pessimism in the design flows. In this paper, we represent the C2Q delays of a flip-flop using artificial neural networks (ANN) and store them in technology libraries. The ANN captures the dependency of the C2Q delay on the data slew, clock slew, output load, setup skew and hold skew. We show that the proposed model computes the C2Q delays with errors less than 3% compared to the SPICE model. Furthermore, using 65 nm foundry library and 15 nm NCSU FreePDK15 models, we demonstrate the effectiveness of the proposed model in removing pessimism of the traditional flip-flop timing model. Additionally, we can employ it to transfer the surplus slack on the output side of a flip-flop to the input side. Thus, we can filter out marginal timing violations and alleviate the timing closure problem using the proposed model.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132424400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ADAPT: An Adaptive Machine Learning Framework with Application to Lithography Hotspot Detection 自适应机器学习框架及其在光刻热点检测中的应用

2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD) Pub Date : 2021-08-30 DOI: 10.1109/MLCAD52597.2021.9531210

M. Alawieh, D. Pan

引用次数: 2

A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing 基于电路注意网络的Actor-Critic学习方法稳健模拟晶体管尺寸

2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD) Pub Date : 2021-08-30 DOI: 10.1109/MLCAD52597.2021.9531156

Yaguang Li, Yishuang Lin, Meghna Madhusudan, A. Sharma, S. Sapatnekar, R. Harjani, Jiang Hu

引用次数: 9