Connectivity-Based Machine Learning Compact Models for Interconnect Parasitic Capacitances

Abstract

A novel neural-networks parasitic extraction modeling methodology for interconnect parasitic capacitances is developed in rule-based extractors. The current rule-based extractors rely on thousands of parasitic capacitance formulas, each covering few or very limited set of interconnect patterns. These formulas also typically suffer from large errors in corner cases. The proposed methodology provides compact cross-section neural-network models that predict parasitic coupling capacitances for many diverse metal arrangements considering metals connectivity. These models significantly improve the accuracy of rule-based extraction methods. Also, they significantly reduce the pattern mismatches in traditional rule-based methods. The inputs to the proposed compact models are: dimensions of a layout pattern, aggressor polygons, and the required victim polygons for a certain process stack. Two different pattern representations are proposed to be used as inputs to neural-networks models: ratio-based and dimensions-based representations. The proposed methodology shows superior characteristics as compared to traditional existing models in four ways. First, it has high pattern coverage. Second, it mitigates the pattern mismatches. Third, it provides compact, descriptive, and accurate cross-section parasitic models. Fourth, it can handle the increasing accuracy requirements in advanced nodes. The proposed methodology is tested over three test chips of 28nm process node with more than 4.8M interconnect structures. The proposed methodology managed to significantly reduce the pattern mismatches and provided outstanding results as compared to field-solvers with an average error < 0.1% and a standard deviation < 3.2%.