Approximate Divider Design Based on Counting-Based Stochastic Computing Division

Shuyuan Yu, Yibo Liu, S. Tan
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引用次数: 2

Abstract

Stochastic computing (SC) promises extremely low cost and energy efficiency for error-tolerant arithmetic operations in many emerging applications such as image processing and deep neural networks. Existing SC-based nonlinear functions like division, however, require highly correlated bit-streams, which does not fit well with the existing SC computing framework in which randomness is required for accuracy. In this paper, we propose a novel SC-based divider design based on recently proposed counting-based stochastic computing scheme, which is much more accurate and faster than traditional SC, and does not depend on randomness of bit-streams for accuracy. We show how such counting-based SC can be applied to nonlinear functions like division. The new divider, called counting-based divider, or CBDIV, exploits both the correlation requirement of existing SC-based division methods and high efficiency of counting-based SC scheme. It essentially combines the best of two worlds in SC and the resulting division operation can be performed as a more efficient partial counting process. Experimental results show that the proposed CBDIV implemented in a 32nm technology node outperforms state of art works by 77.8% in accuracy, 37.1% in delay, 21.5% in area, 50.6% in ADP (area delay product) and 25.9% in power. CBDIV also saves 31.9% in energy consumption when compared to the fixed-point division baseline, and is much more energy efficient than existing SC-based dividers for binary inputs and outputs required in efficient image process implementations. Furthermore, CBDIV with 5-bit precision can even outperform state of art works with 7-bit precision in accuracy by 15.4%. Finally, we compare CBDIV with other state of art SC dividers in contrast stretch application and show that CBDIV can improve the accuracy with 20.6dB in average, which is a huge improvement.
基于计数随机计算除法的近似除法设计
在图像处理和深度神经网络等新兴应用中,随机计算(SC)为容错算术运算提供了极低的成本和能源效率。然而,现有的基于SC的非线性函数(如除法)需要高度相关的比特流,这与现有的SC计算框架(要求随机性以保证准确性)不太适合。在本文中,我们基于最近提出的基于计数的随机计算方案,提出了一种新的基于SC的分频器设计,它比传统的SC更准确和更快,并且不依赖于比特流的随机性。我们展示了这种基于计数的SC如何应用于诸如除法之类的非线性函数。基于计数的除法(CBDIV)既利用了现有基于SC的除法方法的相关性要求,又利用了基于计数的SC方案的高效率。它本质上结合了SC中最好的两个世界,由此产生的除法操作可以作为更有效的部分计数过程来执行。实验结果表明,在32nm技术节点上实现的CBDIV在精度、延迟、面积、ADP(面积延迟产品)和功耗方面分别比现有技术提高了77.8%、37.1%、21.5%和25.9%。与定点除法基线相比,CBDIV还节省了31.9%的能耗,并且在高效图像处理实现所需的二进制输入和输出方面,CBDIV比现有的基于sc的除法节能得多。此外,5位精度的CBDIV甚至比现有的7位精度的精度高出15.4%。最后,我们将CBDIV与其他最先进的SC分频器在对比拉伸应用中进行了比较,结果表明CBDIV平均提高了20.6dB的精度,这是一个巨大的进步。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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