Yaguang Li, Yishuang Lin, Meghna Madhusudan, A. Sharma, S. Sapatnekar, R. Harjani, Jiang Hu
{"title":"A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing","authors":"Yaguang Li, Yishuang Lin, Meghna Madhusudan, A. Sharma, S. Sapatnekar, R. Harjani, Jiang Hu","doi":"10.1109/MLCAD52597.2021.9531156","DOIUrl":null,"url":null,"abstract":"Analog integrated circuit design is highly complex and its automation is a long-standing challenge. We present a reinforcement learning approach to automatic transistor sizing, a key step in determining analog circuit performance. A circuit attention network technique is developed to capture the impact of transistor sizing on circuit performance in an actor-critic learning framework. Our approach also includes a stochastic technique for addressing layout effect, another important factor affecting performance. Compared to Bayesian optimization (BO) and Graph Convolutional Network-based reinforcement learning (GCN-RL), two state-of-the-art methods, the proposed approach significantly improves robustness against layout uncertainty while achieving better post-layout performance. BO and GCN-RL can be enhanced with our stochastic technique to reach solution quality similar to ours, but still suffer from a much slower convergence rate. Moreover, the knowledge transfer in our approach is more effective than that in GCN-RL.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MLCAD52597.2021.9531156","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
Analog integrated circuit design is highly complex and its automation is a long-standing challenge. We present a reinforcement learning approach to automatic transistor sizing, a key step in determining analog circuit performance. A circuit attention network technique is developed to capture the impact of transistor sizing on circuit performance in an actor-critic learning framework. Our approach also includes a stochastic technique for addressing layout effect, another important factor affecting performance. Compared to Bayesian optimization (BO) and Graph Convolutional Network-based reinforcement learning (GCN-RL), two state-of-the-art methods, the proposed approach significantly improves robustness against layout uncertainty while achieving better post-layout performance. BO and GCN-RL can be enhanced with our stochastic technique to reach solution quality similar to ours, but still suffer from a much slower convergence rate. Moreover, the knowledge transfer in our approach is more effective than that in GCN-RL.