量子点元胞自动机中外部能量或内部细胞缺陷的故障建模

IF 1.9 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Debajyoty Banik
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引用次数: 0

摘要

纳米技术使电路更容易出错。使用一种常规方法(如与原始电路的级联门)对顺序可逆电路进行测试需要大量的空间和功率。我提出了一种基于保守逻辑的顺序电路的优越测试策略。这项工作的主要目标是创建一个可测试的顺序电路,在电路面积和其他成本参数方面是紧凑的。我的方法不需要改变原来的电路。因此,使用所提出的方法合并可测试特征不会影响整个电路的复杂性。本文还建立了小功率分子QCA中外部多余能量或内部细胞缺陷的故障卡滞模型。采用该方法对可逆双边缘触发触发器进行了测试。所提出的方法仍然可以应用于量子元胞自动机(QCA)设计中单向故障卡滞的100%故障覆盖率。由于分层技术更可靠和经济,因此设计被分配到实践中。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Fault modeling for external energy or internal cell defect in quantum dot cellular automata

Nanotechnology has made the circuits more susceptible to errors. It takes a lot of space and power to make sequential reversible circuits testable using one of the conventional methods (such as cascading gates with the original circuit). I suggest a superior testing strategy for sequential circuits based on conservative logic. The primary goal of this effort is to create a testable sequential circuit that is compact in terms of circuit area and other cost parameters. My method does not require changing the original circuit. So, incorporating testable features using the proposed method does not affect the complexity of the overall circuit. In this work, stuck-at-fault modeling for external unwanted energy or internal cell defect in low-power molecular QCA is also derived. The reversible double-edge triggered (DET) flip-flop is tested using the suggested approach. The proposed methodology can still be applied to achieve 100% fault coverage for unidirectional stuck-at-fault in quantum cellular automata (QCA) designs. The design is assigned into practice using a layered technique since it is more reliable and economical.

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来源期刊
Microprocessors and Microsystems
Microprocessors and Microsystems 工程技术-工程:电子与电气
CiteScore
6.90
自引率
3.80%
发文量
204
审稿时长
172 days
期刊介绍: Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC). Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.
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