F. Arnaud, Nicolas Planes, O. Weber, V. Barral, S. Haendler, Philippe Flatresse, F. Nyer
{"title":"切换能源效率优化先进的CPU感谢UTBB技术","authors":"F. Arnaud, Nicolas Planes, O. Weber, V. Barral, S. Haendler, Philippe Flatresse, F. Nyer","doi":"10.1109/IEDM.2012.6478970","DOIUrl":null,"url":null,"abstract":"This paper presents the superior performance of UTBB (Ultra-Thin Box and Body) technology for providing high speed at low voltage. We evidence the transistor capability to sustain full forward-body-biasing solution thanks to a planar back-side gate scheme. Silicon measurements on low complexity circuits show that the dynamic power consumption can be reduced by 90% without any speed degradation by simply selecting the appropriate power supply and body bias couple (Vdd; Vbb). A simple switching energy efficiency model is then proposed allowing the (Vdd; Vbb) couple prediction reaching the minimum energy point. Finally, we demonstrate on a full CPU Core implementation with UTBB a total power reduction of -30% and a +40% energy efficiency at identical speed with respect to bulk technology thanks to back side gate biasing efficiency.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":" 71","pages":"3.2.1-3.2.4"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"41","resultStr":"{\"title\":\"Switching energy efficiency optimization for advanced CPU thanks to UTBB technology\",\"authors\":\"F. Arnaud, Nicolas Planes, O. Weber, V. Barral, S. Haendler, Philippe Flatresse, F. Nyer\",\"doi\":\"10.1109/IEDM.2012.6478970\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the superior performance of UTBB (Ultra-Thin Box and Body) technology for providing high speed at low voltage. We evidence the transistor capability to sustain full forward-body-biasing solution thanks to a planar back-side gate scheme. Silicon measurements on low complexity circuits show that the dynamic power consumption can be reduced by 90% without any speed degradation by simply selecting the appropriate power supply and body bias couple (Vdd; Vbb). A simple switching energy efficiency model is then proposed allowing the (Vdd; Vbb) couple prediction reaching the minimum energy point. Finally, we demonstrate on a full CPU Core implementation with UTBB a total power reduction of -30% and a +40% energy efficiency at identical speed with respect to bulk technology thanks to back side gate biasing efficiency.\",\"PeriodicalId\":6376,\"journal\":{\"name\":\"2012 International Electron Devices Meeting\",\"volume\":\" 71\",\"pages\":\"3.2.1-3.2.4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"41\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2012.6478970\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2012.6478970","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 41
摘要
本文介绍了超薄盒体(Ultra-Thin Box and Body, UTBB)技术在低电压下提供高速的优越性能。我们证明了由于平面背面栅极方案,晶体管能够维持完全的正向体偏置解决方案。在低复杂度电路上的硅测量表明,通过简单地选择合适的电源和体偏置耦合器(Vdd;Vbb)。然后提出了一个简单的开关能效模型,允许(Vdd;Vbb)耦合预测达到最小能量点。最后,我们展示了一个完整的CPU核心实现与UTBB,总功耗降低-30%和+40%的能源效率在相同的速度相对于散装技术,由于后门偏置效率。
Switching energy efficiency optimization for advanced CPU thanks to UTBB technology
This paper presents the superior performance of UTBB (Ultra-Thin Box and Body) technology for providing high speed at low voltage. We evidence the transistor capability to sustain full forward-body-biasing solution thanks to a planar back-side gate scheme. Silicon measurements on low complexity circuits show that the dynamic power consumption can be reduced by 90% without any speed degradation by simply selecting the appropriate power supply and body bias couple (Vdd; Vbb). A simple switching energy efficiency model is then proposed allowing the (Vdd; Vbb) couple prediction reaching the minimum energy point. Finally, we demonstrate on a full CPU Core implementation with UTBB a total power reduction of -30% and a +40% energy efficiency at identical speed with respect to bulk technology thanks to back side gate biasing efficiency.