片上网络架构下超维计算的硬件/软件协同探索

IF 1.9 4区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Design & Test Pub Date : 2023-12-01 DOI:10.1109/MDAT.2023.3309733

Junhuan Yang, Lei Yang

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引用次数: 0

摘要

编者按:本文介绍了一种基于神经架构搜索的硬件/软件协同探索框架，旨在优化超维计算(HDC)在片上网络(NoC)架构上的部署。-Mahdi Nikdast，美国科罗拉多州立大学-Miquel Moreto，西班牙巴塞罗那超级计算中心-Masoumeh (Azin) Ebrahimi，瑞典皇家理工学院-Sujay Deb，印度德里IIIT

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Hardware/Software Coexploration for Hyperdimensional Computing on Network-on-Chip Architecture

Editor’snotes: This article introduces a hardware/software coexploration framework based on neural architecture search, aimed at optimizing the deployment of hyperdimensional computing (HDC) on Network-on-Chip (NoC) architecture. —Mahdi Nikdast, Colorado State University, USA —Miquel Moreto, Barcelona Supercomputing Center, Spain —Masoumeh (Azin) Ebrahimi, KTH Royal Institute of Technology, Sweden —Sujay Deb, IIIT Delhi, India

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来源期刊

IEEE Design & Test COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-ENGINEERING, ELECTRICAL & ELECTRONIC

CiteScore

3.80

自引率

5.00%

发文量

期刊介绍： IEEE Design & Test offers original works describing the models, methods, and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews, and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy-efficient design, electronic design automation tools, practical technology, and standards.