{"title":"界面陷阱对InAs隧道场效应管和mosfet IV曲线的影响:全量子研究","authors":"M. Pala, D. Esseni, F. Conzatti","doi":"10.1109/IEDM.2012.6478992","DOIUrl":null,"url":null,"abstract":"We present the first computational study employing a full quantum transport model to investigate the effect of interface traps in nanowire InAs Tunnel FETs and MOSFETs. To this purpose, we introduced a description of interface traps in a simulator based on the NEGF formalism and on a 8×8 k·p Hamiltonian and accounting for phonon scattering. Our results show that: (a) even a single trap can detereorate the inverse sub-threshold slope (SS) of a nanowire InAs Tunnel FET; (b) the inelastic phonon assisted tunneling (PAT) through interface traps results in a temperature dependence of the Tunnel FETs IV characteristics; (c) the impact of interface traps on Ioff is larger in Tunnel FETs than in MOSFETs; (d) interface traps represent a sizable source of device variability.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"1 1","pages":"6.6.1-6.6.4"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"65","resultStr":"{\"title\":\"Impact of interface traps on the IV curves of InAs Tunnel-FETs and MOSFETs: A full quantum study\",\"authors\":\"M. Pala, D. Esseni, F. Conzatti\",\"doi\":\"10.1109/IEDM.2012.6478992\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present the first computational study employing a full quantum transport model to investigate the effect of interface traps in nanowire InAs Tunnel FETs and MOSFETs. To this purpose, we introduced a description of interface traps in a simulator based on the NEGF formalism and on a 8×8 k·p Hamiltonian and accounting for phonon scattering. Our results show that: (a) even a single trap can detereorate the inverse sub-threshold slope (SS) of a nanowire InAs Tunnel FET; (b) the inelastic phonon assisted tunneling (PAT) through interface traps results in a temperature dependence of the Tunnel FETs IV characteristics; (c) the impact of interface traps on Ioff is larger in Tunnel FETs than in MOSFETs; (d) interface traps represent a sizable source of device variability.\",\"PeriodicalId\":6376,\"journal\":{\"name\":\"2012 International Electron Devices Meeting\",\"volume\":\"1 1\",\"pages\":\"6.6.1-6.6.4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"65\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2012.6478992\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2012.6478992","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Impact of interface traps on the IV curves of InAs Tunnel-FETs and MOSFETs: A full quantum study
We present the first computational study employing a full quantum transport model to investigate the effect of interface traps in nanowire InAs Tunnel FETs and MOSFETs. To this purpose, we introduced a description of interface traps in a simulator based on the NEGF formalism and on a 8×8 k·p Hamiltonian and accounting for phonon scattering. Our results show that: (a) even a single trap can detereorate the inverse sub-threshold slope (SS) of a nanowire InAs Tunnel FET; (b) the inelastic phonon assisted tunneling (PAT) through interface traps results in a temperature dependence of the Tunnel FETs IV characteristics; (c) the impact of interface traps on Ioff is larger in Tunnel FETs than in MOSFETs; (d) interface traps represent a sizable source of device variability.