0.13um硅化CMOS技术中esd保护n-MOSFET的布局优化和建模

2008 International Conference on Electronic Packaging Technology & High Density Packaging Pub Date : 2008-07-28 DOI:10.1109/ICEPT.2008.4607003

Jia Yuxi, Li Jiao, Ran Feng, Dian Yang

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引用次数: 4

摘要

本文绘制和制作了大量不同器件尺寸、间距和间隙的CMOS器件，以寻找0.13 um硅化CMOS工艺中静电放电(ESD)保护的优化布局规则。采用TLP(传输线脉冲)测量技术，研究了GGNMOS布局参数对ESD防护能力的影响。本文还提出了一种用于ESD NMOS回吸特性建模的直流模型。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Layout optimization and modeling of an ESD-protection n-MOSFET in 0.13um silicide CMOS technology

In this paper, a lot of CMOS devices with different device dimensions, spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection in 0.13 um Silicide CMOS Technology. The dependences of layout parameters on ESD protection ability of GGNMOS are investigated by using the TLP (transmission line pulsing) measurement technique. A DC model for modeling ESD NMOS snapback characteristics is also presented in this paper.

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2008 International Conference on Electronic Packaging Technology & High Density Packaging

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