A hierarchical approach to cost analysis for next generation semiconductor processes

Introduction of next generation semiconductor technologies gets progressively harder and more expensive with each node in the Semiconductor Industry Association (SIA) roadmap. True to tradition, the 0.1-micron node promises to provide a new set of processing complexities and significant capital investment as well as associated manufacturing costs. We have developed a methodology to analyze different process and equipment alternatives, in order to ultimately reduce the capital investment and overall manufacturing cost of wafers through this process. This approach is hierarchical in nature; in other words, it first aids with analysis of alternatives at a process step level and then these results are incorporated in the analysis of the total wafer and die cost at the macro process flow level. A Visual Basic based tool has been developed to enable this analysis.