{"title":"图像缩放引擎内插算法优化及FPGA实现","authors":"F. Ran, Jing Liu, Meihua Xu","doi":"10.1109/ICEPT.2008.4606980","DOIUrl":null,"url":null,"abstract":"Bi-cubic interpolation algorithm is commonly used in image scaling, but traditional cubic interpolation has its own shortcomings such as complicated computation, long computational time and so on. For these problems, the paper studies traditional cubic kernel function and proposes an optimized algorithm with adjustable coefficients. This algorithm utilizes an modifying coefficient lambda to amend the coefficients in the kernel function, which helps the scaling system choose best algorithm with different images. Then, the superiority is verified by MATLAB simulation and the optimized algorithm is applied to the image scaling engine called scaler through the verification in FPGA.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"11 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Interpolating algorithm optimization and FPGA implementation in image scaling engine\",\"authors\":\"F. Ran, Jing Liu, Meihua Xu\",\"doi\":\"10.1109/ICEPT.2008.4606980\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Bi-cubic interpolation algorithm is commonly used in image scaling, but traditional cubic interpolation has its own shortcomings such as complicated computation, long computational time and so on. For these problems, the paper studies traditional cubic kernel function and proposes an optimized algorithm with adjustable coefficients. This algorithm utilizes an modifying coefficient lambda to amend the coefficients in the kernel function, which helps the scaling system choose best algorithm with different images. Then, the superiority is verified by MATLAB simulation and the optimized algorithm is applied to the image scaling engine called scaler through the verification in FPGA.\",\"PeriodicalId\":6324,\"journal\":{\"name\":\"2008 International Conference on Electronic Packaging Technology & High Density Packaging\",\"volume\":\"11 1\",\"pages\":\"1-4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 International Conference on Electronic Packaging Technology & High Density Packaging\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEPT.2008.4606980\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEPT.2008.4606980","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Interpolating algorithm optimization and FPGA implementation in image scaling engine
Bi-cubic interpolation algorithm is commonly used in image scaling, but traditional cubic interpolation has its own shortcomings such as complicated computation, long computational time and so on. For these problems, the paper studies traditional cubic kernel function and proposes an optimized algorithm with adjustable coefficients. This algorithm utilizes an modifying coefficient lambda to amend the coefficients in the kernel function, which helps the scaling system choose best algorithm with different images. Then, the superiority is verified by MATLAB simulation and the optimized algorithm is applied to the image scaling engine called scaler through the verification in FPGA.