High speed package design and electrical performance analysis

More and more high-speed data transmission formats such as rapid IO, hyper transport, Gigabit Ethernet, Serial ATA etc. are becoming prevalent. As substrate interconnection density and channel data rate are getting increasingly higher, various 3D effects, crosstalk, and discontinuity - induced ISI are playing a much more important role, for both signal channels and power distribution networks . The substrate interconnection structures are becoming the major bandwidth constraint for most of the package designer. As data rates continue to increase, transitioning to solder bump or Au stud bump flip-chip interconnects or low-loss substrate materials results in excessive cost. It is therefore increasingly important to provide a high performance and low-cost packaging solution. The aim of this paper is to proposal a design solution of normal plastic ball grid array (PBGA) package for high speed devices. The electrical simulation method of the effects of variation of package design parameters such as signal path structure, wire bonding, through hole via, ball placement tactic and plating stub are highlighted. The conclusion of this paper is recommendation for high-speed package electrical design.