Advanced platform-level clock jitter and drift analysis

Platform clock plays a critical role for digital systems with high-speed serial links. Platform-level reference clock performance analysis is required for all system reference clock architectures to support different platform configurations. The paper presents the advanced platform-level clock jitter and drift methodology being often used by system engineers to guarantee the integrity of platform designs. The best known methods of platform-level clock jitter analysis from the clock sources to receivers due to different jitter characteristics in different clock distribution branches are presented. The novel platform-level cascaded PLL analysis for drift calculation and drift budgeting methodology are introduced.