决定Ge p-和n- mosfet在高Ns区迁移率的物理机制以及原子平面GeOx/Ge界面对迁移率的改善

Rui Zhang, Po-Chin Huang, Ju-Chin Lin, M. Takenaka, S. Takagi
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引用次数: 22

摘要

对具有不同衬底取向和gex /Ge接口质量的Ge p-和n- mosfet进行了霍尔测量。研究发现,在高表面载流子浓度(Ns)或高法向场下,Ge mosfet的有效迁移率显著降低,部分原因是由于Ge的价带和导带内大量的界面态导致了Ns的损失。GeOx/Ge界面粗糙度是限制高Ns迁移率的另一个原因。结果表明,室温等离子体后氧化可以实现具有原子平面的GeOx/Ge界面的Al2O3/GeOx/Ge栅极叠层。具有这些界面的Ge mosfet提供了创纪录的高效空穴和电子迁移率,克服了Si在低和高Ns区域的普遍迁移率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Physical mechanism determining Ge p- and n-MOSFETs mobility in high Ns region and mobility improvement by atomically flat GeOx/Ge interfaces
Hall measurements have been carried out for the Ge p-and n-MOSFETs with different substrate orientations and GeOx/Ge interface qualities. It is found that the significant reduction of effective mobility in high surface carrier concentration (Ns) or high normal field in Ge MOSFETs is attributed partly to the Ns loss due to large amounts of interface states inside the valence and conduction bands of Ge. The GeOx/Ge interface roughness is another reason limiting the high Ns mobility. It has been revealed that room temperature plasma post oxidation can realize Al2O3/GeOx/Ge gate stacks with atomically-flat GeOx/Ge interfaces. Ge MOSFETs with these interfaces have provided record high effective hole and electron mobility, which overcome the Si universal mobility in both low and high Ns regions.
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