{"title":"热循环下焊点反向相容性的仿真与分析","authors":"Ning Ye-xiang, Pan Kai-lin, L. Ni","doi":"10.1109/ICEPT.2008.4606994","DOIUrl":null,"url":null,"abstract":"In this paper, the backward compatibility solder joints were chosen in simulation of perimeter PBGA272 assembly. A double-symmetric plane FE model of a PBGA272 was established using the software ANSYS. Based on the maximum von Mises stress and von Mises strain, the position of the most danger solder joints were obtained under thermal cycle with the temperature condition from -40degC to 125degC (JESD22-A104-B Condition G) , Viz. the inner (1#) solder joint and the outside (6#) solder joint are the two key solder joints which are the easiest to failure. On the basis of above analysis, the geometry parameters of the chosen assembly are optimized by design of experiment (DOE). The factors included PCB size, PCB thickness, chip size, chip thickness, substrate size, substrate thickness, solder height and solder radius. The simulating results have shown that substrate thickness (factor F), solder radius (factor H) and solder height (factor G) performed the main factors. The optimal scheme is F3H2G1C2D1E2B3A2 (substrate thickness 0.7 mm, solder radius 0.38 mm, solder height 0.4 mm, chip size 2.54 mm, chip thickness 0.4 mm, substrate size 13.5 mm, PCB thickness 1.8 mm and PCB size 15 mm) by comprehensively considered with every factorpsilas effect.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"101 1","pages":"1-6"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Simulation and analysis for backward compatibility of solder joints under thermal cycle\",\"authors\":\"Ning Ye-xiang, Pan Kai-lin, L. Ni\",\"doi\":\"10.1109/ICEPT.2008.4606994\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the backward compatibility solder joints were chosen in simulation of perimeter PBGA272 assembly. A double-symmetric plane FE model of a PBGA272 was established using the software ANSYS. Based on the maximum von Mises stress and von Mises strain, the position of the most danger solder joints were obtained under thermal cycle with the temperature condition from -40degC to 125degC (JESD22-A104-B Condition G) , Viz. the inner (1#) solder joint and the outside (6#) solder joint are the two key solder joints which are the easiest to failure. On the basis of above analysis, the geometry parameters of the chosen assembly are optimized by design of experiment (DOE). The factors included PCB size, PCB thickness, chip size, chip thickness, substrate size, substrate thickness, solder height and solder radius. The simulating results have shown that substrate thickness (factor F), solder radius (factor H) and solder height (factor G) performed the main factors. The optimal scheme is F3H2G1C2D1E2B3A2 (substrate thickness 0.7 mm, solder radius 0.38 mm, solder height 0.4 mm, chip size 2.54 mm, chip thickness 0.4 mm, substrate size 13.5 mm, PCB thickness 1.8 mm and PCB size 15 mm) by comprehensively considered with every factorpsilas effect.\",\"PeriodicalId\":6324,\"journal\":{\"name\":\"2008 International Conference on Electronic Packaging Technology & High Density Packaging\",\"volume\":\"101 1\",\"pages\":\"1-6\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 International Conference on Electronic Packaging Technology & High Density Packaging\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEPT.2008.4606994\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEPT.2008.4606994","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
本文选择后向兼容焊点进行了周长PBGA272组装仿真。利用ANSYS软件建立了PBGA272的双对称平面有限元模型。根据最大von Mises应力和von Mises应变,在温度为-40℃~ 125℃(JESD22-A104-B条件G)的热循环条件下,得到了最危险焊点的位置,即内(1#)焊点和外(6#)焊点是最容易失效的两个关键焊点。在此基础上,通过实验设计对所选组件的几何参数进行了优化。影响因素包括PCB尺寸、PCB厚度、芯片尺寸、芯片厚度、衬底尺寸、衬底厚度、焊点高度和焊点半径。仿真结果表明,衬底厚度(F因子)、焊料半径(H因子)和焊料高度(G因子)是影响焊接性能的主要因素。综合考虑各因素的影响,最佳方案为F3H2G1C2D1E2B3A2(衬底厚度0.7 mm,焊料半径0.38 mm,焊料高度0.4 mm,芯片尺寸2.54 mm,芯片厚度0.4 mm,衬底尺寸13.5 mm, PCB板厚度1.8 mm, PCB板尺寸15 mm)。
Simulation and analysis for backward compatibility of solder joints under thermal cycle
In this paper, the backward compatibility solder joints were chosen in simulation of perimeter PBGA272 assembly. A double-symmetric plane FE model of a PBGA272 was established using the software ANSYS. Based on the maximum von Mises stress and von Mises strain, the position of the most danger solder joints were obtained under thermal cycle with the temperature condition from -40degC to 125degC (JESD22-A104-B Condition G) , Viz. the inner (1#) solder joint and the outside (6#) solder joint are the two key solder joints which are the easiest to failure. On the basis of above analysis, the geometry parameters of the chosen assembly are optimized by design of experiment (DOE). The factors included PCB size, PCB thickness, chip size, chip thickness, substrate size, substrate thickness, solder height and solder radius. The simulating results have shown that substrate thickness (factor F), solder radius (factor H) and solder height (factor G) performed the main factors. The optimal scheme is F3H2G1C2D1E2B3A2 (substrate thickness 0.7 mm, solder radius 0.38 mm, solder height 0.4 mm, chip size 2.54 mm, chip thickness 0.4 mm, substrate size 13.5 mm, PCB thickness 1.8 mm and PCB size 15 mm) by comprehensively considered with every factorpsilas effect.