M. Jeong, S. Joe, B. Jo, Ho-Jung Kang, J. Bae, Kyoung-Rok Han, Eun-seok Choi, G. Cho, Sung-Kye Park, Byung-Gook Park, Jong-Ho Lee
{"title":"具有管型多晶硅沟道结构的三维堆叠NAND闪存器件中陷阱的表征","authors":"M. Jeong, S. Joe, B. Jo, Ho-Jung Kang, J. Bae, Kyoung-Rok Han, Eun-seok Choi, G. Cho, Sung-Kye Park, Byung-Gook Park, Jong-Ho Lee","doi":"10.1109/IEDM.2012.6479010","DOIUrl":null,"url":null,"abstract":"Trap density (D<sub>it</sub>) was extracted for the first time in 3-D stacked NAND flash memory with the tube-type poly-Si channel structure. We verified extracted D<sub>it</sub> with conductance method and charge pumping method in 32 nm floating gate (FG) NAND flash memory device. In 3-D stacked NAND flash memory device, the D<sub>it</sub> extracted by conductance method was 1~2×10<sup>12</sup> cm<sup>-2</sup>eV<sup>-1</sup> in E<sub>c</sub>-E<sub>T</sub> of 0.15~0.35 eV. The simulation results of I<sub>BL</sub>-V<sub>CG</sub> and C-V<sub>CG</sub> based on the D<sub>it</sub> were conformable with the measurement data. Then we investigated the effects of program/erase (P/E) cycling stress on 1/f noise in NAND flash devices. Finally, we extracted firstly the position of a trap generating random telegraph noise (RTN) by considering cylindrical coordinate and pass cell resistance in the 3-D stacked NAND flash memory cell.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"34 1","pages":"9.3.1-9.3.4"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Characterization of traps in 3-D stacked NAND flash memory devices with tube-type poly-Si channel structure\",\"authors\":\"M. Jeong, S. Joe, B. Jo, Ho-Jung Kang, J. Bae, Kyoung-Rok Han, Eun-seok Choi, G. Cho, Sung-Kye Park, Byung-Gook Park, Jong-Ho Lee\",\"doi\":\"10.1109/IEDM.2012.6479010\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Trap density (D<sub>it</sub>) was extracted for the first time in 3-D stacked NAND flash memory with the tube-type poly-Si channel structure. We verified extracted D<sub>it</sub> with conductance method and charge pumping method in 32 nm floating gate (FG) NAND flash memory device. In 3-D stacked NAND flash memory device, the D<sub>it</sub> extracted by conductance method was 1~2×10<sup>12</sup> cm<sup>-2</sup>eV<sup>-1</sup> in E<sub>c</sub>-E<sub>T</sub> of 0.15~0.35 eV. The simulation results of I<sub>BL</sub>-V<sub>CG</sub> and C-V<sub>CG</sub> based on the D<sub>it</sub> were conformable with the measurement data. Then we investigated the effects of program/erase (P/E) cycling stress on 1/f noise in NAND flash devices. Finally, we extracted firstly the position of a trap generating random telegraph noise (RTN) by considering cylindrical coordinate and pass cell resistance in the 3-D stacked NAND flash memory cell.\",\"PeriodicalId\":6376,\"journal\":{\"name\":\"2012 International Electron Devices Meeting\",\"volume\":\"34 1\",\"pages\":\"9.3.1-9.3.4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2012.6479010\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2012.6479010","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Characterization of traps in 3-D stacked NAND flash memory devices with tube-type poly-Si channel structure
Trap density (Dit) was extracted for the first time in 3-D stacked NAND flash memory with the tube-type poly-Si channel structure. We verified extracted Dit with conductance method and charge pumping method in 32 nm floating gate (FG) NAND flash memory device. In 3-D stacked NAND flash memory device, the Dit extracted by conductance method was 1~2×1012 cm-2eV-1 in Ec-ET of 0.15~0.35 eV. The simulation results of IBL-VCG and C-VCG based on the Dit were conformable with the measurement data. Then we investigated the effects of program/erase (P/E) cycling stress on 1/f noise in NAND flash devices. Finally, we extracted firstly the position of a trap generating random telegraph noise (RTN) by considering cylindrical coordinate and pass cell resistance in the 3-D stacked NAND flash memory cell.