M. Jeong, S. Joe, B. Jo, Ho-Jung Kang, J. Bae, Kyoung-Rok Han, Eun-seok Choi, G. Cho, Sung-Kye Park, Byung-Gook Park, Jong-Ho Lee
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Characterization of traps in 3-D stacked NAND flash memory devices with tube-type poly-Si channel structure
Trap density (Dit) was extracted for the first time in 3-D stacked NAND flash memory with the tube-type poly-Si channel structure. We verified extracted Dit with conductance method and charge pumping method in 32 nm floating gate (FG) NAND flash memory device. In 3-D stacked NAND flash memory device, the Dit extracted by conductance method was 1~2×1012 cm-2eV-1 in Ec-ET of 0.15~0.35 eV. The simulation results of IBL-VCG and C-VCG based on the Dit were conformable with the measurement data. Then we investigated the effects of program/erase (P/E) cycling stress on 1/f noise in NAND flash devices. Finally, we extracted firstly the position of a trap generating random telegraph noise (RTN) by considering cylindrical coordinate and pass cell resistance in the 3-D stacked NAND flash memory cell.
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