具有管型多晶硅沟道结构的三维堆叠NAND闪存器件中陷阱的表征

M. Jeong, S. Joe, B. Jo, Ho-Jung Kang, J. Bae, Kyoung-Rok Han, Eun-seok Choi, G. Cho, Sung-Kye Park, Byung-Gook Park, Jong-Ho Lee
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引用次数: 15

摘要

首次在具有管型多晶硅通道结构的3-D堆叠NAND闪存中提取了陷阱密度(Dit)。利用电导法和电荷泵送法在32nm浮栅(FG) NAND闪存器件中验证了提取Dit的可行性。在3-D堆叠NAND闪存器件中,电导法提取的Dit在0.15~0.35 eV的Ec-ET中为1~2×1012 cm-2eV-1。基于Dit的IBL-VCG和C-VCG仿真结果与实测数据吻合较好。然后研究了程序/擦除(P/E)循环应力对NAND闪存器件中1/f噪声的影响。最后,我们首先在三维堆叠NAND闪存单元中考虑圆柱坐标和通道单元电阻,提取产生随机电报噪声(RTN)的陷阱的位置。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Characterization of traps in 3-D stacked NAND flash memory devices with tube-type poly-Si channel structure
Trap density (Dit) was extracted for the first time in 3-D stacked NAND flash memory with the tube-type poly-Si channel structure. We verified extracted Dit with conductance method and charge pumping method in 32 nm floating gate (FG) NAND flash memory device. In 3-D stacked NAND flash memory device, the Dit extracted by conductance method was 1~2×1012 cm-2eV-1 in Ec-ET of 0.15~0.35 eV. The simulation results of IBL-VCG and C-VCG based on the Dit were conformable with the measurement data. Then we investigated the effects of program/erase (P/E) cycling stress on 1/f noise in NAND flash devices. Finally, we extracted firstly the position of a trap generating random telegraph noise (RTN) by considering cylindrical coordinate and pass cell resistance in the 3-D stacked NAND flash memory cell.
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