具有超薄硅通道和25nm栅极长度的高性能FDSOI器件的应力记忆

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI:10.1109/IEDM.2005.1609392

D. V. Singh, J. Sleight, J. Hergenrother, Z. Ren, K. Jenkins, O. Dokumaci, L. Black, J.B. Chang, H. Nakayama, D. Chidambarrao, R. Venigalla, J. Pan, W. Natzle, B. Tessier, A. Nomura, J. Ott, M. Ieong, W. Haensch

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引用次数: 15

摘要

我们首次报道了应力记忆(SM)以及SM和双应力衬里(DSL)对具有凸源/漏极结构和通道厚度为18nm的高性能全耗尽超薄通道器件的综合影响。SM可以显著提高驱动电流和迁移率，与使用DSL方法获得的结果相当。在SM过程中，应力传递到通道可能通过多通道发生，随着身体变瘦而变得更有效。结合SM和DSL的净增益大大大于单独使用每种技术所获得的增益

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Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths

We report for the first time, the effect of stress memorization (SM), and the combined effects of SM and dual stress liner (DSL) on high performance fully-depleted ultra-thin channel devices with a raised source/drain architecture and channel thickness of 18nm. SM results in significant drive current and mobility enhancement, comparable to that obtained using the DSL approach. Stress transfer to the channel during SM likely occurs through the poly-gate, becoming more effective as the body is thinned. Combining SM and DSL results in a net gain that is substantially larger than that obtained using each technique separately

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IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

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