L. Grenouillet, M. Vinet, J. Gimbert, B. Giraud, J. Noel, Q. Liu, P. Khare, M. Jaud, Y. Le Tiec, R. Wacquez, T. Levin, P. Rivallin, S. Holmes, S. Liu, K. Chen, O. Rozeau, P. Scheiblin, E. Mclellan, M. Malley, J. Guilford, A. Upham, R. Johnson, M. Hargrove, T. Hook, S. Schmitz, S. Mehta, J. Kuss, N. Loubet, S. Teehan, M. Terrizzi, S. Ponoth, K. Cheng, T. Nagumo, A. Khakifirooz, F. Monsieur, P. Kulkarni, R. Conte, J. Demarest, O. Faynot, W. Kleemeier, S. Luning, B. Doris
{"title":"具有双STI的UTBB FDSOI晶体管，用于20nm及以下节点的多vt策略","authors":"L. Grenouillet, M. Vinet, J. Gimbert, B. Giraud, J. Noel, Q. Liu, P. Khare, M. Jaud, Y. Le Tiec, R. Wacquez, T. Levin, P. Rivallin, S. Holmes, S. Liu, K. Chen, O. Rozeau, P. Scheiblin, E. Mclellan, M. Malley, J. Guilford, A. Upham, R. Johnson, M. Hargrove, T. Hook, S. Schmitz, S. Mehta, J. Kuss, N. Loubet, S. Teehan, M. Terrizzi, S. Ponoth, K. Cheng, T. Nagumo, A. Khakifirooz, F. Monsieur, P. Kulkarni, R. Conte, J. Demarest, O. Faynot, W. Kleemeier, S. Luning, B. Doris","doi":"10.1109/IEDM.2012.6478974","DOIUrl":null,"url":null,"abstract":"We introduce an innovative dual-depth shallow trench isolation (dual STI) scheme for Ultra Thin Body and BOX (UTBB) FDSOI architecture. Since in the dual STI configuration wells are isolated from one another by the deepest trenches, this architecture enables a full use of the back bias while staying compatible with both standard bulk design and conventional SOI substrates. We demonstrate in 20nm ground rules that we are able to tune Vt by more than 400mV, that transistor performance can be boosted by up to 30% and that Ioff can be controlled over 3 decades by allowing more than VDD/2 to be applied on the back gate.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"61","resultStr":"{\"title\":\"UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below\",\"authors\":\"L. Grenouillet, M. Vinet, J. Gimbert, B. Giraud, J. Noel, Q. Liu, P. Khare, M. Jaud, Y. Le Tiec, R. Wacquez, T. Levin, P. Rivallin, S. Holmes, S. Liu, K. Chen, O. Rozeau, P. Scheiblin, E. Mclellan, M. Malley, J. Guilford, A. Upham, R. Johnson, M. Hargrove, T. Hook, S. Schmitz, S. Mehta, J. Kuss, N. Loubet, S. Teehan, M. Terrizzi, S. Ponoth, K. Cheng, T. Nagumo, A. Khakifirooz, F. Monsieur, P. Kulkarni, R. Conte, J. Demarest, O. Faynot, W. Kleemeier, S. Luning, B. Doris\",\"doi\":\"10.1109/IEDM.2012.6478974\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We introduce an innovative dual-depth shallow trench isolation (dual STI) scheme for Ultra Thin Body and BOX (UTBB) FDSOI architecture. Since in the dual STI configuration wells are isolated from one another by the deepest trenches, this architecture enables a full use of the back bias while staying compatible with both standard bulk design and conventional SOI substrates. We demonstrate in 20nm ground rules that we are able to tune Vt by more than 400mV, that transistor performance can be boosted by up to 30% and that Ioff can be controlled over 3 decades by allowing more than VDD/2 to be applied on the back gate.\",\"PeriodicalId\":6376,\"journal\":{\"name\":\"2012 International Electron Devices Meeting\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"61\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2012.6478974\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2012.6478974","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below
We introduce an innovative dual-depth shallow trench isolation (dual STI) scheme for Ultra Thin Body and BOX (UTBB) FDSOI architecture. Since in the dual STI configuration wells are isolated from one another by the deepest trenches, this architecture enables a full use of the back bias while staying compatible with both standard bulk design and conventional SOI substrates. We demonstrate in 20nm ground rules that we are able to tune Vt by more than 400mV, that transistor performance can be boosted by up to 30% and that Ioff can be controlled over 3 decades by allowing more than VDD/2 to be applied on the back gate.
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