低功耗应用的65nm cmos技术

A. Steegen, R. Mo, R. Mann, M. Sun, M. Eller, G. Leake, D. Vietzke, A. Tilke, F. Guarín, A. Fischer, T. Pompl, G. Massey, A. Vayshenker, W. Tan, A. Ebert, W. Lin, W. Gao, J. Lian, J. Kim, P. Wrschka, J. Yang, A. Ajmera, R. Knoefler, Y. Teh, F. Jamin, J. Park, K. Hooper, C. Griffin, P. Nguyen, V. Klee, V. Ku, C. Baiocco, G. Johnson, L. Tai, J. Benedict, S. Scheer, H. Zhuang, V. Ramanchandran, G. Matusiewicz, Y. Lin, Y. Siew, F. Zhang, L. S. Leong, S. L. Liew, K. Park, K. Lee, D. Hong, S. Choi, E. Kaltalioglu, S.O. Kim, M. Naujok, M. Sherony, A. Cowley, A. Thomas, J. Sudijohno, T. Schiml, J. Ku, I. Yang
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引用次数: 44

摘要

本文提出了一种65nm低功耗技术,提供双栅氧化工艺,标称工作电压为1.2V的多个Vt器件,具有低k介电和0.676mum2和0.54 mum2 SRAM单元的九级分层Cu互连线后端工艺,分别优化了性能和密度。该技术的重点是低成本、工艺简单和降低功耗。一种栅极电介质具有低至15pA/mum的场效应漏电流,并具有优异的可靠性特性。此外,在标称电压下,n/ pts在关闭电流为7nA/mum时实现了725/343muA/mum的竞争驱动电流。通过使用迁移率增强技术,在不增加工艺复杂性的情况下,在7nA/mum关闭电流下,fet的性能又提高了13%。优化的NiSi工艺和高角度、低剂量光晕植入物有助于减少结漏和GIDL电流
本文章由计算机程序翻译,如有差异,请以英文原文为准。
65nm cmos technology for low power applications
This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676mum2 and 0.54mum 2 SRAM cells, optimized for performance and density, respectively. The key focus of this technology has been low cost, process simplicity and power reduction. A gate dielectric with an nfet leakage current as low as 15pA/mum and with exceptional reliability characteristics has been demonstrated. Moreover, competitive drive current has been achieved, 725/343muA/mum at an off current of 7nA/mum for n/pfets at nominal voltage. A pfet performance enhancement of an additional 13% at 7nA/mum off current was achieved by using mobility enhancement techniques without adding process complexity. An optimized NiSi process and high angle, low dose halo implants contribute to the reduced junction leakage and GIDL current
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