Productivity improvement of stack package line through die bonding process & scheme optimization

To conform to the ever-emerging market demand, stacked memory devices have been more widely utilized. The stacking method also reduces the cost of electronical components through the way that stacking could fully utilize currently on-hand equipment without any new investment. While, starting from late 2003, flash memory manufacturers begin experience capacity degradation, specifically with multiple loop-back workflows induced by stack CSP devices. By analyzing the process of stacking, the industrypsilas practice considers the control of assembly cost largely depends on the improvement of overall line productivity, specifically the critical bottle-neck area of die bonding. This presentation intends to critically describe the methodology and procedures used by Intelpsilas stack CSP assembly factory, which finally results innovative projects targeting above said productivity improvements. The authors use TRIZ, an inventive problem solving theory and application tool, to analyze and abstract the major contradictions and then sketch out possible solutions. As a result of the applications, the overall stack CSP assembly factorypsilas productivity increased to a record-high of 340%, far above the industry average, and supports Intelpsilas stack CSP assembly factory more efficient than benchmarking world-class companies ever since. The authors of this paper wishes the methodology on productivity and design flexibility at Intelpsilas stack CSP assembly factory could possibly be proliferated, so as to help achieve productivity and capability maximum output throughout the industry.