DRAM单元扩展到40nm的挑战

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI:10.1109/IEDM.2005.1609344

W. Müller, G. Aichmayr, W. Bergner, E. Erben, T. Hecht, C. Kapteyn, A. Kersch, S. Kudelka, F. Lau, J. Luetzen, A. Orth, J. Nuetzel, T. Schloesser, A. Scholz, U. Schroeder, Alexander Sieck, Andrea Spitzer, M. Strasser, Peng Wang, S. Wege, R. Weis

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引用次数: 87

摘要

本文综述了DRAM缩制至40nm的概念、现状和挑战。讨论的技术是DRAM单元电容器结构和材料，以及单元晶体管结构

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Challenges for the DRAM cell scaling to 40nm

This paper reviews the concepts, status and challenges for the DRAM scaling down to 40nm. The technologies that are discussed are the DRAM cell capacitor structures and materials, as well as the cell transistor structures

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IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

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