{"title":"数字密集型接收机设计:机遇与挑战","authors":"R. Nanda, D. Markovic","doi":"10.1109/MDT.2012.2214756","DOIUrl":null,"url":null,"abstract":"This article discusses the trade-offs involved in the implementation of a highly digital receiver and then describes a direct-sampling architecture which provides a wide range of runtime adaptability by varying parameters such as sample rate, filter order, and interpolation factor.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2214756","citationCount":"0","resultStr":"{\"title\":\"Digitally intensive receiver design: opportunities and challenges\",\"authors\":\"R. Nanda, D. Markovic\",\"doi\":\"10.1109/MDT.2012.2214756\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article discusses the trade-offs involved in the implementation of a highly digital receiver and then describes a direct-sampling architecture which provides a wide range of runtime adaptability by varying parameters such as sample rate, filter order, and interpolation factor.\",\"PeriodicalId\":50392,\"journal\":{\"name\":\"IEEE Design & Test of Computers\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1109/MDT.2012.2214756\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Design & Test of Computers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MDT.2012.2214756\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Design & Test of Computers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MDT.2012.2214756","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Digitally intensive receiver design: opportunities and challenges
This article discusses the trade-offs involved in the implementation of a highly digital receiver and then describes a direct-sampling architecture which provides a wide range of runtime adaptability by varying parameters such as sample rate, filter order, and interpolation factor.