{"title":"客座编辑介绍:智能硅的片上结构","authors":"M. Tehranipoor, L. Winemberg","doi":"10.1109/MDT.2012.2212533","DOIUrl":null,"url":null,"abstract":"This special issue presents novel on-chip structures for monitoring aging and variations in the circuit, analyzing circuit operation condition's impact on aging and performance degradation, agingaware power/performance tuning, interoperability and optimization for SerDes, and finally using onchip power monitors for detection of hardware Trojans in integrated circuits. Five papers were selected for publication in this special issue.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"6-7"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2212533","citationCount":"0","resultStr":"{\"title\":\"Guest Editors' introduction: On-chip structures for smarter silicon\",\"authors\":\"M. Tehranipoor, L. Winemberg\",\"doi\":\"10.1109/MDT.2012.2212533\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This special issue presents novel on-chip structures for monitoring aging and variations in the circuit, analyzing circuit operation condition's impact on aging and performance degradation, agingaware power/performance tuning, interoperability and optimization for SerDes, and finally using onchip power monitors for detection of hardware Trojans in integrated circuits. Five papers were selected for publication in this special issue.\",\"PeriodicalId\":50392,\"journal\":{\"name\":\"IEEE Design & Test of Computers\",\"volume\":\"29 1\",\"pages\":\"6-7\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1109/MDT.2012.2212533\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Design & Test of Computers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MDT.2012.2212533\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Design & Test of Computers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MDT.2012.2212533","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Guest Editors' introduction: On-chip structures for smarter silicon
This special issue presents novel on-chip structures for monitoring aging and variations in the circuit, analyzing circuit operation condition's impact on aging and performance degradation, agingaware power/performance tuning, interoperability and optimization for SerDes, and finally using onchip power monitors for detection of hardware Trojans in integrated circuits. Five papers were selected for publication in this special issue.
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