V. Champac, Julio Vazquez Hernandez, S. Barcelo, Roberto Gómez, C. Hawkins, J. Segura
{"title":"纳米技术中卡断故障的检测","authors":"V. Champac, Julio Vazquez Hernandez, S. Barcelo, Roberto Gómez, C. Hawkins, J. Segura","doi":"10.1109/MDT.2012.2205609","DOIUrl":null,"url":null,"abstract":"Failure analysis and fault modeling of integrated circuits have always been fields that require continuous revision and update as manufacturing processes evolve. This paper discusses the new face of the well-known transistor stuck-open fault model in modern nanometer technologies and proposes new detection methods that improve the robustness of tests.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"80-91"},"PeriodicalIF":0.0000,"publicationDate":"2012-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2205609","citationCount":"14","resultStr":"{\"title\":\"Testing of Stuck-Open Faults in Nanometer Technologies\",\"authors\":\"V. Champac, Julio Vazquez Hernandez, S. Barcelo, Roberto Gómez, C. Hawkins, J. Segura\",\"doi\":\"10.1109/MDT.2012.2205609\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Failure analysis and fault modeling of integrated circuits have always been fields that require continuous revision and update as manufacturing processes evolve. This paper discusses the new face of the well-known transistor stuck-open fault model in modern nanometer technologies and proposes new detection methods that improve the robustness of tests.\",\"PeriodicalId\":50392,\"journal\":{\"name\":\"IEEE Design & Test of Computers\",\"volume\":\"29 1\",\"pages\":\"80-91\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1109/MDT.2012.2205609\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Design & Test of Computers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MDT.2012.2205609\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Design & Test of Computers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MDT.2012.2205609","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Testing of Stuck-Open Faults in Nanometer Technologies
Failure analysis and fault modeling of integrated circuits have always been fields that require continuous revision and update as manufacturing processes evolve. This paper discusses the new face of the well-known transistor stuck-open fault model in modern nanometer technologies and proposes new detection methods that improve the robustness of tests.
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