A Look at IEEE P1687 Internal JTAG (IJTAG)

h IN LIGHT OF the recent introduction of IEEE’s P1687, Internal JTAG (IJTAG) standard, the first half of this special issue is dedicated to familiarizing our readers with some of the experiences and drawbacks, implementations and troubleshooting challenges, and other economic and technical implications that the proposed standard raises. Such an evolution from the older established technologies and practices necessitates that we extract from relevant work done by industry professionals and high-profile researchers to help bring our readers up to speed. This is what we hope to have accomplished here. In true Design and Test form, we have also included some variety on the back end of the issue, to round out the P1687 articles with an international vantage on different approaches to addressing faults and defects at different levels of abstraction and integration, including the threats posed by hardware Trojans. We begin our issue on the topic of IJTAG with an article by authors in industry and academia from Texas and California that provide a new perspective on FPGA-based testers in light of IJTAG. They show that for each IC or board design, embedded FPGA testers must be reconfigured, proving difficult for creating standardized observation systems. The authors propose a methodology that effectively allows embedded vectors to automatically be retargeted to the TAP port of the FPGA. Ultimately, they show how to create a standardized Command, Control, and Observation system. Second, we present a paper from the AlcatelLucent Labs in Villarceaux, France, and New Jersey, which outlines some shortcomings in traditional vector-level control of dynamic IJTAG operations. The authors introduce state machine-level control, which forms a more comprehensive solution allowing a greater potential usage of IJTAG. Our next article, compiled by researchers in Tallinn, Estonia, proposes a new instrumentation infrastructure, based on IJTAG, which supports fault management that automatically collects and delivers detection information to operating systems. The authors specifically demonstrate the efficiency of this infrastructure. Next, we receive a breather from the deeply technical side of things, in favor of viewing the effects of the latest IJTAG on the fiscal element of our industry. Martin Keim, from Mentor Graphics, explores three industry scenarios, showing the cost of adopting IJTAG versus the costs of sticking with older, traditional systems. Then we step out of the IJTAG box and begin our latter half of the issue with an analysis of the clustering of defects on silicon wafers. A group of authors from Southeast Asia present a new, flexible three-stage automation tool aimed at improving cluster analysis, while also offering sufficient devicespecific customization to allow the accommodation of a wide variety of product types. Next, researchers from Huazhong University, China, reiterate concerns in the security of highcapacity storage of critical sensitive information, and counter these concerns by implementing integrity protection and off-chip memory encryption using the Advanced Encryption StandardVGalois/ Counter Mode. This approach is also shown to lower the overhead of memory and performance.