Design and Development of Fine Pitch Copper/Low-K Wafer Level Package

Copper (Cu)/low-dielectric constant (K) structures are desired choices for advanced integrated circuits (ICs) as the IC technology moving towards fine pitch, high speed, increased integration and high performance. Copper interconnects with low-k dielectric material improve the performance of ICs by reducing interconnect the RC delay, the cross talk between the adjacent metal lines and the power loss. However, the packaging of Cu/low-k IC device is a challenge for the packaging industry to integrate these devices without any failure during assembly and reliability. The current work presents, 1) the finite element model (FEM) based parametric study on Cu/low-K wafer level package (WLP) reliability and stresses on Cu/low-K layers, and 2) experimental validation of WLP reliability by fabricating the test chips. FEM modeling and simulation results have shown that high aspect ratio interconnects, thinner die, and thinner printed circuit board can reduce the stress in low-k layer and enhance the board level interconnect reliability. Test chip of 7 mm ? 7 mm size is designed with 128 input/output (I/O) off-chip interconnects at 300-?m pitch in two depopulated rows using redistribution layers (RDL). Test chips are fabricated on 200-mm-diameter wafer with blanket black diamond (BD) low-K layers structure. Two different Pb free solder interconnects, thick copper column of 100 ?m height with SnAg solder cap and SnAg solder bump of 150 ?m height with 5-?m-thick copper under bump metallurgy (UBM), are fabricated. The Cu/low-K test chips are assembled onto a two layer high glass transition temperature (Tg) FR-4 substrate using two different types of no-flow underfills (NFU) to build the test vehicles and assembled test vehicles are subjected to various JEDEC standard reliability tests, and related failure analysis is carried out. Cu/low-k WLP with copper column interconnects without no-flow underfill passed 1000 h high-temperature storage (HTS) test, and passed the JEDEC drop test with no-flow underfill. Thin die test vehicles of Cu column interconnects with no-flow underfill and extra solder shown better thermal cycling (TC) performance and the board level TC performance can be improved further using thicker RDL.