振动条件下全周阵列对电子组件机械可靠性影响的数值研究

IF 0.7 4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics International Pub Date : 2023-07-28 DOI:10.1108/mi-02-2023-0014

Mohammad A. Gharaibeh

{"title":"振动条件下全周阵列对电子组件机械可靠性影响的数值研究","authors":"Mohammad A. Gharaibeh","doi":"10.1108/mi-02-2023-0014","DOIUrl":null,"url":null,"abstract":"\nPurpose\nThis paper aims to compare and evaluate the influence of package designs and characteristics on the mechanical reliability of electronic assemblies when subjected to harmonic vibrations.\n\n\nDesign/methodology/approach\nUsing finite element analysis (FEA), the effect of package design-related parameters, including the interconnect array configuration, i.e. full vs perimeter, and package size, on solder mechanical stresses are fully addressed.\n\n\nFindings\nThe results of FEA simulations revealed that the number of solder rows or columns available in the array, could significantly affect solder stresses. In addition, smaller packages result in lower solder stresses and differing distributions.\n\n\nOriginality/value\nIn literature, there are no papers that discuss the effect of solder array layout on electronic packages vibration reliability. In addition, general rules for designing electronic assemblies subjected to harmonic vibration loadings are proposed in this paper.\n","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":" ","pages":""},"PeriodicalIF":0.7000,"publicationDate":"2023-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A numerical investigation on the influence of full vs perimeter arrays on the mechanical reliability of electronic assemblies under vibration\",\"authors\":\"Mohammad A. Gharaibeh\",\"doi\":\"10.1108/mi-02-2023-0014\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"\\nPurpose\\nThis paper aims to compare and evaluate the influence of package designs and characteristics on the mechanical reliability of electronic assemblies when subjected to harmonic vibrations.\\n\\n\\nDesign/methodology/approach\\nUsing finite element analysis (FEA), the effect of package design-related parameters, including the interconnect array configuration, i.e. full vs perimeter, and package size, on solder mechanical stresses are fully addressed.\\n\\n\\nFindings\\nThe results of FEA simulations revealed that the number of solder rows or columns available in the array, could significantly affect solder stresses. In addition, smaller packages result in lower solder stresses and differing distributions.\\n\\n\\nOriginality/value\\nIn literature, there are no papers that discuss the effect of solder array layout on electronic packages vibration reliability. In addition, general rules for designing electronic assemblies subjected to harmonic vibration loadings are proposed in this paper.\\n\",\"PeriodicalId\":49817,\"journal\":{\"name\":\"Microelectronics International\",\"volume\":\" \",\"pages\":\"\"},\"PeriodicalIF\":0.7000,\"publicationDate\":\"2023-07-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics International\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://doi.org/10.1108/mi-02-2023-0014\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics International","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1108/mi-02-2023-0014","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

摘要

目的本文旨在比较和评估在谐波振动下，封装设计和特性对电子组件机械可靠性的影响。设计/方法/方法使用有限元分析（FEA），充分解决了封装设计相关参数对焊料机械应力的影响，包括互连阵列配置，即全周长与周长以及封装尺寸。结果有限元分析模拟结果表明，阵列中可用的焊料行或列的数量可能会显著影响焊料应力。此外，更小的封装导致更低的焊接应力和不同的分布。原创性/价值在文献中，没有论文讨论焊料阵列布局对电子封装振动可靠性的影响。此外，本文还提出了在谐波振动载荷作用下设计电子组件的一般规则。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A numerical investigation on the influence of full vs perimeter arrays on the mechanical reliability of electronic assemblies under vibration

Purpose This paper aims to compare and evaluate the influence of package designs and characteristics on the mechanical reliability of electronic assemblies when subjected to harmonic vibrations. Design/methodology/approach Using finite element analysis (FEA), the effect of package design-related parameters, including the interconnect array configuration, i.e. full vs perimeter, and package size, on solder mechanical stresses are fully addressed. Findings The results of FEA simulations revealed that the number of solder rows or columns available in the array, could significantly affect solder stresses. In addition, smaller packages result in lower solder stresses and differing distributions. Originality/value In literature, there are no papers that discuss the effect of solder array layout on electronic packages vibration reliability. In addition, general rules for designing electronic assemblies subjected to harmonic vibration loadings are proposed in this paper.

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来源期刊

Microelectronics International 工程技术-材料科学：综合

CiteScore

1.90

自引率

9.10%

发文量

审稿时长

>12 weeks

期刊介绍： Microelectronics International provides an authoritative, international and independent forum for the critical evaluation and dissemination of research and development, applications, processes and current practices relating to advanced packaging, micro-circuit engineering, interconnection, semiconductor technology and systems engineering. It represents a current, comprehensive and practical information tool. The Editor, Dr John Atkinson, welcomes contributions to the journal including technical papers, research papers, case studies and review papers for publication. Please view the Author Guidelines for further details. Microelectronics International comprises a multi-disciplinary study of the key technologies and related issues associated with the design, manufacture, assembly and various applications of miniaturized electronic devices and advanced packages. Among the broad range of topics covered are: • Advanced packaging • Ceramics • Chip attachment • Chip on board (COB) • Chip scale packaging • Flexible substrates • MEMS • Micro-circuit technology • Microelectronic materials • Multichip modules (MCMs) • Organic/polymer electronics • Printed electronics • Semiconductor technology • Solid state sensors • Thermal management • Thick/thin film technology • Wafer scale processing.